International Symposium on System-on-Chip
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Enabling Technologies for System-on-Chip Development

"The Biggest Challenges in System-on-Chip Integration" - Summary of panel discussion

Chairman:
Prof. Jari Nurmi, Tampere Univ. of Tech.

Participants:
Prof. Jan Rabaey,UC Berkeley
Prof. Heinrich Meyr, RWTH Aachen
Dr. Ravi Subramanian, MorphICs, Inc.
Dr. Vojin Zivojnovic, AXYS Design Automation GmbH
Mr. Oz Levia, Improv Systems, Inc.
Introduction

Before the actual panel discussion took place, all the participants were asked to give a short introduction to the topic by describing their opinion on the biggest challenges in SoC integration.

Prof. Rabaey

Professor Rabaey started his presentation with a humorous example based on the system complexity increases and IC fabrication volume growths. He had calculated that, with the current exponential growth rates, all the energy in our galaxy would be consumed by integrated circuits in the next 180 years. This example was to show that the improvement of energy efficiency seriously lags behind the rapid advances in integration technologies. Prof. Rabaey also brought out the trinity of architectures, platforms, and languages, and described the defining and developing of the programmer's model to be the principal challenge in the near future.

Mr. Levia

At the beginning of his presentation, Mr. Levia stated that currently the System-on-Chip implementations are either small and simple designs, e.g, revisions of existing systems, or complex large volume products. SoC integration has not yet come available for the masses. This is due to the fact that designing a complex SoC system is an expensive multi-year project which requires experienced design teams and dedicated IP-blocks. Mr. Levia defined SoC as integration of multiple types of blocks, namely programmable parts, I/O, memory, and analog blocks. This integration has proven to be a non-trivial task because it is rather difficult to get the different data- and control oriented parts to work together properly. The shrinking feature sizes also cause some timing and power consumption problems. Mr. Levia wanted to underline the fact that SoC is not a board on a die; instead, different design and partitioning rules and methodologies must be applied. In addition to these technical difficulties, some mental blocks were also introduced. It seems that many people are reluctant to accept new technologies and design methodologies. This resistance to change can be seen for example in the slow adoption of IP reuse. Considering all these economical, technological, and emotional obstacles, it can be said that currently SoC is just not delivering. As a viable solution and a reasonable future direction, Mr. Levia suggested the use of programmable, configurable, and scaleable platforms. This platform concept is closely connected to the use of real IP, which consists of virtual software IP, hard I/O blocks, memory, analog blocks, and different platform configurations.

Prof. Meyr

In professor Meyr's opinion, the greatest challenge in SoC integration is the design gap. This means that mastering the design of complex chips is ever more difficult because the development of design tools and methodologies is considerably slower than the improvements in integration technologies. Moreover, in order to be able to do SoC designs, one must master algorithms, design methodologies, and architectures. Since no-one can adequately handle all the three, a close interaction between designers and design teams is required. Despite all these problems, Prof. Meyr sees that SoC has a future, especially in the field of communications.

Dr. Subramanian

Doctor Subramanian agreed with Prof. Rabaey on the view about the biggest problem associated to SoC integration, namely the energy efficiency. He presented the exponential graphs describing Shannon's and Moore's laws which decipt the growth of algorithm complexity and processor performance, and compared them to the merely linear increase in battery capasity. As the second most important obstacle, Dr. Subramanian saw the verification. The role of proper verification is, due to the high design and manufacturing costs, essential in SoC integration. The economical factors and the great expectations of the industry oblige the SoC designs to be right the first time; no iteration rounds can be afforded. This implies that the target application must be well-known. Furthermore, the importance of heterogenous fabrics and design tools and flows should not be underestimated. Dr. Subramanian explained that SoC integration is very profit-driven, time-to-market being the most crucial constraint set by the industry. All efforts should be focused on high-level designs and subsystems since they get most of the money and interest. Suitable application areas for SoC are for example communications, networking, and media processing.

Dr. Zivojnovic

The last speaker, Dr. Vojin Zivojnovic, started his introduction by trying to define System-on-Chip. Even though the definition is somewhat vague, some characteristic aspects of the design process can be found. In SoC integration, many design teams with different backgrounds are trying to work together. This is obviously difficult since the teams are used to different design flows, tools, and communication practices. The process even more complicated by the fact that all the various subsystems and blocks must be designed, verified, and completed simultaneously, in parallel fashion. Dr. Zivojnovic also mentioned that the problems faced in SoC integration are almost the same as were in the case of Multi-Chip-Module designs.

Discussion

The panel discussion started with a question by Prof. Nurmi about improving the energy efficiency. Prof. Rabaey replied that the key is to think the power issues early on in the design process. Energy consumption should be considered in the conception level, before the architecture specification. Furthermore, algorithm and system level partitioning play a major role in this matter. The big importance of top-down design style was also emphasized.

The next question, again presented by Prof. Nurmi, was about education in communication between the engineers. Prof. Meyr replied that one should learn the basics of all aspects of SoC design, i.e., algorithm design, DSP, etc. Creating complex systems requires interaction between the engineers, and this can be learned only by practice, not by theory. Prof. Meyr also emphasized the role of professors in SoC design education. Prof. Rabaey agreed about the interaction and continued by saying that co-operation, not individualism is needed. However, universities, being very result-oriented, show a rather bad example on what comes to team-work. Prof. Meyr commented that the lack of co-operation is not a privilege of the universities; it can also be seen in the industry.

Next, the roles of the universities and the industry were discussed. Prof. Meyr said that the industry gives money to the universities which, in return, provide research results and educated work force. Universities also act as testbeds for new methods, technologies, and methodologies. This is very beneficial to the industry since, contrary to the universities, failed experiments are not acceptable. Prof. Nurmi reminded about the non-existent tools and asked whether the universities should make them. Mr. Levia thought that the breakthrough will not come from the universities. He suggested that especially the undergraduates are not capable of developing anything new. Prof. Rabaey disagreed by stating that the industry has too short sight, whereas this tool dilemma demands new problem solving techniques and long-term efforts which can only originate in the universities. As examples of similar incidents in the past he mentioned logic synthesis and Cossap, neither of which were developed by the industry. Dr. Subramanian underlined the importance of analysis skills and competition in the academic world. He also told that there are some universities which teach and stimulate these vital skills. To sum this theme up, Prof. Meyr concluded that universities are to take risks exploring new ideas and methods. However, strong interaction and co-operation with the industry is needed when new tools are being developed.

Mr. Levia told in his introduction that only the 'rich and famous' can afford to do SoC design. The audience asked him to clarify the expression a bit. Mr. Levia explained that SoCs are huge; they contain a large amount of different types of blocks in addition to the software running on top of everything. Since the design process, let alone the possible failure, is enormously expensive, SoC integration can only be applied to mass-volume products. As a follow-up question, audience inquired about the differencies in business models associated to SoC. Mr. Levia expressed that there are too many degrees of freedom in SoC design, e.g., freedom in software, power, and platform choices. He said that some of the variables must be made constants, and blocks must be re-used in order to be able to apply SoC integration also to low-volume products.

The next question from the audience was about tools and methods; are the old ASIC design tools and methods obsoleted by the SoC integration. Mr. Levia made it quite clear that this indeed is the case. Design and Behavioral Compiler, for example, are no longer relevant since they participate in only a small part of the design flow. Subsequently, Dr. Subramanian expressed his opinion on the question about the 'rich and famous'. He stated that only the five most successful companies, i.e., the market leaders, in every area of business can afford to do SoC design. Next, the conversation turned into the clash of interests between the system houses and the silicon vendors. Prof. Rabaey explained that the design companies would like their systems to be used in many different applications whereas the silicon foundries would prefer making a new chip for each new application. In conclusion, Dr. Zivojnovic predicted that megacells will be the basic building blocks in SoC design and that there will be some battle over IP between the system houses and the silicon vendors.

The next topic of conversation, the role of MCM technology in SoC design, was again a question from the audience. Professor Rabaey started off by saying that there is no fundamental difference between SoC and MCM. The choice between the two is a compromise between cost and design complexity. Mr. Levia added that sometimes, e.g., when using an external memory is too slow, SoC is the only viable alternative. Dr. Zivojnovic reasoned that SoC is cheaper than MCM. The conclusion was that the high-level design problems are identical for the both technologies.

The penultimate question was about the future of SoC. Prof. Meyr answered that communications, more specifically quaranteeing the Quality-of-Service, will be the primary driving force in SoC's near future. Mr. Levia brought out the fact that soon, as the limits of the transistor technology are reached, a change of paradigm is inevitable. Finally, Doctor Zivojnovic inquired what will come after the video, 3D video maybe?

The last issue for discussion was the change in manufacturing chain caused by the new SoC integration. With older technologies, the rivalry between the foundries was healthy and open. Now, however, since there are only a few SoC-capable vendors, the competition is very limited or even non-existent. It was asked how will the companies not in market leader position survive this new situation. Prof. Rabaey told that a strong multi-discipline knowledge is a practical means of survival. As a conclusion to the panel he, yet again, highlighted the essence of co-operation and interaction in SoC design.