International Symposium on System-on-Chip
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Fully Programmable Systems: The Future of Application Specific Systems

Sharad Malik, Princeton University

A variety of diverse pressures are shaping how we will design digital systems in the near future. Shrinking geometries into the deep submicron range raise electrical design challenges that make it impossible to use existing methodologies for application specific system design. In addition, the corresponding exponential increase in the number of devices per chip results in a complexity problem which by itself threatens to cripple existing design methodologies. Finally, increased non-recurring engineering costs for masks and design tools force designs to be limited to higher volume products. All of these point to a gradual reduction of designs done using conventional ASIC (application specific integrated circuits) design methodology.

I will first argue as to why this points to an increase in systems that contain programmable components that are specialized for a specific application domain, while at the same time providing design flexibility that permits the same device to be used for a range of related products and also generations of a product. A key aspect of these systems is the use of on-chip multi-processing systems - made possible by silicon availability and required by product performance requirements. I will then describe the MESCAL (Modern Embedded Systems: Compilers, Architectures and Languages) project that is focussed on developing a complete set of design tools as well as methodology for the design of fully programmable systems of the future.

Compiler Technology for Configurable Processor Architectures

Monica Lam, Stanford University

SOC technology has made it feasible to design unique processor architectures to deliver the required performance of embedded applications at minimal cost and power. Many of the architectural concepts developed previously for supercomputers such as VLIW, SIMD and processor array organizations have become applicable to the embedded domain. To minimize the software development time and hence the time to market, it is critical that an effective compiler and all the associated software development tools be available. This talk describes the challenges and solutions in creating a compiler system that generates compilers for configurable processors. In particular, we will describe the fundamental technology for handling parallelism at both the instruction and processor levels.

Solutions for Communication and Design Reuse in Gigascale Systems-on-Chip

Hannu Tenhunen, Royal Institute of Technology

The future System-on-Chip (SoC) implementations in year 2005 and beyond will be made in technologies with minimum feature size in the range of 0.05 - 0.10 um. The application specific integrated circuits will be up to a billion transistor systems operating at 1 GHz in very demanding self-induced noise conditions. The design is no more a block level problem, but a global communication issue. The key elements in achieving functional silicon with high operating frequency and low power consumption will be the on-chip communications and interconnects. One of the bottlenecks in developing complex circuits is what is called 'the productivity gap'. The designer is not able to design systems-on-chip utilizing the full capacity that the manufacturing technologies can provide. One way to circumvent the situation has been the growing use of Intellectual Property (IP) blocks or Virtual Components (VC) as they are also called. However, more gain in productivity is needed. It is noteworthy that the productivity gain has to be achieved mainly in the digital circuitry domain, since the analog content of SoC designs cannot be grown very much. Here, the functional blocks, processors and memories can be accessed as commercial or legacy VCs. A flexible but efficient interblock communication architecture is what remains on the designer's wish list. The complex systems-on-chip are essentially heterogeneous multiprocessor systems integrated with miniaturized communication networks, bringing up again the importance of communication and synchronization issues. The next step towards SoC integration is to move on to communication platform design and to on-chip heterogeneous multiprocessor based integration platforms.

The IMPACT Compiler Infrastructure for Future DSP/Embedded Systems

Roger Bringmann, Lucent Technologies

The IMPACT Compiler infrastructure is a new platform for developing future compilers for DSP/Embedded Systems. It contains a powerful combination of interprocedural pointer analysis and memory access analysis to enable aggressive optimization of memory references. A BDD based condition and predicate analysis enables aggressive optimization of program decision logic and program control flow. A schedule-time transformation framework allows automatic application of code optimizations that are traditionally performed by hand. A flexible intrinsic support facility allows state of the art EPIC compilers to efficiently support DSP and embedded system specific hardware features. This presentation gives an overview of these key features of the new infrastructure.

SoC or SoP?

A Balanced Approach!
Evan Davidson, IBM

System-on-a-Chip (SoC) has received much publicity during the last few years. It is a goal promulgated by the semiconductor industry that is used to tout the future circuit densities and chip sizes projected by the International Technology Roadmap for Semiconductors (ITRS). The stated ITRS goals represent many challenges for developers some of which have no known solutions. So what happens if the ITRS goals (note: they are not predictions) do not materialize or if they are prohibitively expensive? Is there an alternative? Fortunately there is one; it is called System-on-a-Package (SoP)!

Until recently, most product engineers considered the electronic package as a simple commodity that allowed interconnections for signals and power to chips. In addition, the package was a treated as a mechanical support structure that provided protection and cooling. Given this meager role, the package was considered to be a necessary but not a value-add set of components in most electronic systems. Nowadays and for many reasons, this attitude about electronic packaging is rapidly changing. The incentives for a better outlook for packaging are based upon higher system frequencies, support of more I/O and wiring capacity, better cooling, embedded passives and lower overall packaged electronics (chips plus packages) costs. The summation of all of these attributes is the SoP.

This presentation will straddle the line between chips and packages by discussing prudent tradeoffs. In particular, the performance and cost differences between large chips and small multi-chip modules (MCMs) will be depicted. Furthermore, the significance of the current heavy worldwide investment in organic packaging and its ability to provide superior application solutions at lower prices will be portrayed. The hoped for result will be to engender an increasing respect for the value potential for electronic packages in a world of semiconductors.

Reconfigurable Computing Platforms

Steve Guccione, Xilinx

In the last decade and a half, Field Programmable Gate Arrays (FPGAs) have grown from simple devices with a few hundred programmable logic gates to densities beyond one million gates. This growth in density has led to an ever-expanding area of application for these devices. From their early use as simple interface or "glue" logic, FPGAs have moved on to become popular platforms for implementing system bus interfaces, including industry standards such as PCI. As device density has surpassed one million gates, FPGA co-processing in data-intensive applications such as Digital Signal Processing (DSP) and networking has become commonplace. The recent announcement of the Virtex II FPGA + CPU device from Xilinx, as well as similar announcements from other vendors, indicate that the trend toward single chip FPGA + CPU processing will continue. And with ten million gate devices under development, it is expected that more system functionality, including more general-purpose processing, will continue to migrate into the FPGA. While much of this type of coprocessing can also be accomplished with fixed Application Specific Integrated Circuit (ASIC) hardware, the ability to reprogram FPGA devices, even in system, opens up new opportunities for system design. Reconfigurable logic provides new methods for increasing performance, decreasing power consumption and increasing system functionality. Along with these new benefits come challenges, particularly in the area of software design tools. Tools such as Xilinx's JBits point the way toward providing a single unified environment for programming CPUs, configuring and reconfiguring hardware resources and providing integrated debug support for the single chip reconfigurable systems of the future.

DSP-Based System-on-Chip Roadmap to the Future

Yves Masse, Texas Instruments

In early 90's, TI offered capability to its DSP users to develop system logic around the DSP core though "customizable DSPs". Currently customizable DSPs represent more than 75% of the DSPs shipped by TI. Furthermore, the number of cores and the amount of logic and the amount of memory to be integrated in a single chip is increasing. For example, TI is currently proposing more complex processor combination: OMAP is an Open Multimedia Application platform consisting of a DSP core and a Microcontroller core or other DSPs include 2 or 4 DSP cores. In the future, The number of cores, logic and memory to be integrated on chip will continue to increase driven by performance needs, lower power dissipation needs and smaller process geometries. During this presentation, we will analyze the reasons to integrate more DSPs in SOC, we will also look at the different challenges faced by this integration namely the methodology to define and architect such SOC, to develop, validate, and ensure fast ramp-up of such complex SOC and to develop and debug S/W on such complex SOC.

Scalable and Customizable VLIW for Embedded Applications

Andrew Jones and Roger Shepherd, STMicroelectronics

The talk will consist of two parts, a presentation of the STMicroelectronics SOC interconnect technology, and a presentation of ST's customisable VLIW technology.

1. In the past decade ST has delivered a number of highly integrated chips aimed at the digital video market place. A key facet in reducing time to market is the development and promotion of internal standards and technologies which promote low-cost re-use of IP and systems. The talk will illustrate this by describing the development of tools which automatically generate of high performance interconnects, tools which formally prove that an IP integration is correct, and the development of structures which allow the debugging of real-time software involving the interactions of multiple on-chip IP blocks.

2. The ST200/Lx is not just another VLIW architecture. It represents a framework which allows the rapid customisation of a VLIW architecture targeted to a particular application. The presentation will talk about the framework and the ST200 the first instance of an Lx processor.

C++ in SoC Design

Joachim Kunkel, Synopsys

While C/C++ has been used for system level design in the past, it has always suffered from the lack of widely accepted mechanism to describe hardware concepts like hardware data types, concurrency or abstract interfaces. This has made it difficult to share C/C++ based system level descriptions among different groups.

The Open SystemC Initiative, which was launched in September of 1999, represents a major step towards providing a language standard for C/C++ based system level design.

SystemC uses the C++ class mechanism to provide the concepts designers need to effectively design hardware and software systems. In doing so, it enhances the expressiveness of the C++ language while maintaining its compatibility with a standard C++ compiler. Furthermore, SystemC can be downloaded from the Web free of charge, effectively enabling the exchange of system level models and executable specifications.

This talk will discuss the evolution of C/C++ based design tools and flows in the context of SystemC.

A Reconfigurable Communications Processor Architecture

Wolfgang Hoeflich, Chameleon Systems

A new type of reconfigurable communications processor (RCP) architecture was introduced in May 2000 by Chameleon Systems, San Jose, CA. This presentation will introduce the architecture and design flow of the RCP processor and how it relates to the implementation of advanced communications algorithms.

Compared with traditional, fixed DSP architectures, the RCP is a flexible parallel processing architecture. The RCP is aimed at high performance signal processing applications, such as 3G basestations and multi-channel communications applications, for example VoIP and DSL.

This presentation describes the main building blocks of the architecture (Reconfigurable Processing Fabric, programmable interconnects, programmable I/O, RISC processor, Memory Controller, DMA, PCI). System-level features such as the instant reconfiguration will be discussed.

As this architecture requires a new development process, the tool flow into an RCP will be presented. The tool flow involves RTL synthesis, chip P&R, C-code compilation and linking, as well as the verification process using RTL simulation and C debugging tools.

Finally, an applications example, the Turbo Coder, will be shown. The Turbo coders one of the key building blocks used in the IS2000 (UMTS) 3rd generation wireless applications. We will analyze bandwidth, memory and real-estate considerations, as well as the benefits of instant reconfiguration of the RCP. A performance comparison will show the advantages over traditional DSP implementations.

Implementing Complex SoPC designs in Altera PLDs

This presentation outlines recent developments by Altera in the FPGA technology and key SoPC system components. The key component is the Excalibur Family which incorporates microprocessors integral to the PLD array. In this presentation we will focus on the soft processor Nios and how that was used to create an MP3 player design in a single PLD.

An outline of the design philosophy, approach and implementation will be presented as well as a short demonstration of the final result.


The Configurable Processor Comes of Age

Tensilica, the leading supplier of configurable microprocessor cores will present its Xtensa processor development environment.

The Xtensa processor is ideally suited for SoC design.

  1. Greater flexibility. For example fully synthesisable RTL source as a standard feature and a full GNU based software environment
  2. Easier and faster cost/performance analysis so that you can architect the best hardware/software combination for your unique application
  3. A complete embedded processor development environment so that hardware and software are developed in synch and in minimum time.
  4. Highest code density so that memory requirements are minimised
  5. Integration of functions within the processor which are traditionally implemented with additional IP blocks.

This results in lower overall silicon cost, fewer integration problems and easier verification