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Enabling Technologies for System-on-Chip Development
"Future Trends in HW/SW Partitioning for SoC"
- Summary of panel discussion
Prof. Jari Nurmi, Tampere University of Technology
Prof. Monica Lam, Stanford University
Prof. Sharad Malik, Princeton University
Dr. Steven Guccione, Xilinx, Inc.
Mr. Joachim Kunkel, Synopsys, Inc.
Pete Cumming, Texas Instruments, Inc.
Ahmed Shihab, Altera, Corp.
Before the actual discussion started, each participant gave a short introduction to the topic.
First, Steve Guccione defined the SoC as a single chip solution of an embedded system which may consists of microprocessor(s) and custom logic. SoC solutions are used when performance, size, weight, or power consumption is an issue. Traditionally, the hardware parts of a system have been designed using a CAD tool, and the software parts with programming languages. SoC designs, however, introduce a set of new problems. In addition to the huge costs of a SoC, the debugging and HW/SW integration are also very difficult. This implies that new tools that support joint HW/SW specification, simulation, emulation, prototyping, and debugging, are needed. Dr. Guccione proposed the use of high-level languages as a viable solution to this design dilemma. Dr. Guccione stated that the main requirements for SoC hardware are flexibility, repairability, high density, rapidly decreasing cost, and competitive performance. Dr. Guccione's view is that reconfigurable (FPGA) devices are the solution of future SoC designs. The currently available FPGAs have already high density, good performance and reasonably low cost, which makes them ideal for SoC designs. Dr. Guccione ended his introduction by summarising the biggest problem in SoC to be the debugging and the final system integration.
The second speaker, Monica Lam, stressed out the importance of HW/SW partitioning and proposed an instruction set architecture (ISA) compiler to be a solution. In her opinion, the architecture is a compromise between HW and SW, and moreover, SW should be though to be on top of HW. She suggested that in HW/SW partitioning one should first generate the actual architecture, then map the architecture to hardware and finally make specific instructions that use effectively the special HW functions in SW. The specialized hardware, which can be automatically generated with tools, offers significant speed-up through HW-mapped user-defined data types and function primitives. In the future compilers will support C++ classes and automatic register allocation. However, a lot of work is still to be done in the field of compilers, especially in finding and utilizing the inherent parallelism in various applications.
Joachim Kunkel discussed a new system level description language called SystemC. The idea in SystemC is to use the same description language throughout the whole design process, starting from algorithm design and evaluation to HW and SW implementation. he use of the same language to describe both software and hardware parts of the same system will help us to delay the most difficult decision in the design cycle: where to partition the system. Mr. Kunkel would keep the SW and HW design together as long as possible using SystemC as a design language. He focused on the importance of design re-use and presented the future vision, in which all the architecture pieces are ready and only the connections between them need to be made. He was quick to point out that this is not reality at the moment. As an academic issue Mr. Kunkel presented a vision of a tool that could be used to evaluate different HW/SW partitioning solutions and synthesize the optimal result to HW and SW parts.
Mr. Cumming proposed a paradigm based on developing a library of IP blocks, thoroughly tested and proved. The components can be either HW or SW. Design should be a HW/SW co-design with flexibility and appropriate degree of openness to updates. There are two things that define whether a component should be implemented in HW or SW: 1) optimal solution vs. re-usable solution 2) integration level. Other requirements for the components are low power consumption, low cost and good upgradeability. Future efforts must be focused on standardization and optimization of these IPs. By using standard IP blocks we'll lose part of the high efficiency and specificity that could be achieved with other methods, but also we'll reduce the time-to-market, by making the process simpler. SoC applications run over operating system and a framework which correspondingly utilizes components and different drivers. Mr. Cumming stated that: "Portable, abstract programming is the issue". Compared to FPGA solutions, platform based solutions offer better operating systems. He presented a four-layer design view, which comprised of driver (bottom), component, operating system & firmware and application (top) layers. Everything under the application layer could be considered to be a part of an IP-library. This approach has tight HW coupling in the driver level. The tools of the future would be IP evaluation and selection tools. The key idea of this platform approach is the cheap HW with powerful engine. Texas Instruments' OMAP (Open Multimedia Application Platform) is a realization of this vision. A set of HW IP blocks are selected to accompany a specific RISC and/or DSP processor on the SoC. An operating system, such as EPOC, is ported to run on this processor. OMAP also includes HW drivers that enable easy use of the IP block resources on application level.
S. Malik thinks that HW/SW partitioning is only one of the challenges in SoC. The actual partitioning problem, according to Mr. Malik, is how the application concurrency can be mapped to implementation concurrency efficiently in size, speed, and power. To reach this the specification must use heterogeneous forms of computation, the implementation needs to be efficient and the communication overhead needs to be obtained by analysis and simulation. He also claimed that explicit concurrency specification is better than implicit specifications.
A. Shihab expressed the time-to-market problem. In his opinion FPGAs are a good solution for SoC designs. They have several advantages over ASICs such as short design time, lower cost, large density, and easy and fast prototyping. For FPGAs the IP integration presents one challenge.
After the initial presentations the actual discussion started. The discussion areas were the correct design language, verification and validation, FPGA-based solutions, and the role of the compilers. The discussion on these topics is summarised below.
The first issue was brought up by Prof. Lam, asking Prof. Malik which language he would use to describe the parallelism in an application. He answered that probably the optimal solution would be to use a mix of different languages, depending on what one is trying to describe. Thus, each part of the application specification would use the best suitable language available to express its natural concurrency in the simplest way. Mr. Kunkel argued that doing things in that way will increase the complexity of the design job, and stressed the need for automating such things like analyzing and describing the parallelism of any given application. Software tools will probably do it faster and better - cheaper at least. Xilinx and Altera representatives replied that the complexity of such software would be quite high, considering the huge gap between hardware internals and the syntax of general purpose languages like C/C++. It was suggested that C could be used and that it could be written so that concurrency remains. It was, however, found to be difficult to separate C language structures into hardware. SystemC is an extension (library) to regular C++. The benefit of using this class library is that it lets designers express such hardware-oriented concepts as concurrency, parallelism, ports, wires and reactivity. Agreeing on a standard library will allow IP providers and system designers to use one dialect of C++, thus allowing interoperability, and provide a common platform on which to build synthesis, hardware/software co-design and verification tools. One of the biggest benefits in C-like syntax is that it is a language that is widely used and that people are familiar with. Prof. Lam said that the point in using C/Fortran/etc. is in using an already existing language, with all that it involves, i.e., readily available tools, proven methodology, large amount of pre-existing users, etc. Often, different methods might have historical load, i.e., a "design culture", which might be a good as well as a bad thing. However, history should also be appreciated as an experience. Another proposed language was Matlab. Matlab is probably the best language for algorithm development and description, while SystemC can describe the system architecture and functionality very efficiently. Matlab's drawback is insufficient performance in simulations.
Verification and Validation
Verification and validation was found to have become the most challenging task in SoC design. Especially the tremendous increase in system complexity was mentioned when, e.g., 3G mobile systems are designed. If HW was verified as SW it would require extremely big resources. One solution is to distinct the working reusable blocks from the other blocks since these blocks need not be verified, thus reducing the testing cost. However, the interfaces between the blocks have to be always verified. There is no clear solution to this problem. The challenge can be made somewhat easier by using standard interfaces and design methods, defined for example by VSIA. In a way this approach operates similarly as in IP, where along with the block one also buys the debug services. Another solution was found between ASIC and FPGA approaches. When verification in ASIC is very expensive and time consuming, the same verification can be done real time in-place for FPGAs. Since modern uPs are becoming more and more effective it means that in SoC the number of processors increases. Therefore, SW reliability is of high importance.
The Role of Compilers
Both HW and SW parts of a modern system are becoming more and more complex. It is getting harder to describe those systems so that they work correctly. Also the productivity of the designers does not grow as fast as the silicon technology capabilities, i.e., number of gates in an ASIC and the amount of MIPS in a processor. One solution to this problem is to raise the abstraction level of the design description. This approach sets a lot of new requirements for the compilers. For example, in SW development, the first compilers only transformed an assembly language description to binary machine language. The advent of higher level description languages, such as C and C++, have forced compilers to become much more intelligent. Prof. Monica Lam proposed instruction set architecture (ISA) specific compilers to be a solution to HW/SW partitioning problems. In her opinion, the compiler is the interconnect between HW and SW. She suggested that in HW/SW partitioning one should first try to find the actual architecture, map the architecture to hardware and then make specific instructions that use effectively the special HW elements in SW. By doing this, the partitioning would be more of a top-down issue. From system architecture point of view SW would be on top of HW. The compiler would use application specific instructions to access application specific HW computation units.
The Role of FPGAs
This section of the discussion was focused on the future of the FPGA architecture. It was agreed that there will always be gap between ASICs and FPGAs if utmost performance is required. However, the role of full custom design was seen to be diminishing, especially in large SoC systems. It seems that there are two different approaches to the problem of future SoC design: on the one hand, the FPGAs; on the other hand, the IPs and dedicated hardware blocks. Programmable devices offer the invaluable benefit of being able to modify the hardware if the functional specification is changed or bugs in fixed HW blocks or in the software are found. In addition to the high performance, the advantage of dedicated IP blocks and cores is the easy integration and verification of the whole system, as the individual blocks are already separately verified. One alternative is to abandon the strict division between programmable and fixed implementations, and to find a compromise which utilizes both FPGAs and dedicated blocks. Modern FPGAs already tend to include more and more dedicated internal blocks, such as processor cores, bus interfaces, memories etc. Conversely, programmable logic structures can be included in ASIC designs as IP blocks. Thus, as the granularity of FPGAs keeps increasing, the difference between a future FPGA and a SoC ASIC can be very vague or even nonexistent. In any scenario, however, the need of reconfigurable logic in a SoC is evident as profits strongly depend on time-to-market and the system specification can change when the device is already in fabrication.