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Francky Catthoor

Francky Catthoor received the engineering degree and a Ph.D. in electrical engineering from the Katholieke Universiteit Leuven, Belgium in 1982 and 1987 respectively. From September 1983 till June 1987 he has been a researcher in the area of VLSI design methodologies for Digital Signal Processing, with Prof. Hugo De Man and Prof. Joos Vandewalle as Ph.D. thesis advisors. Since 1987, he has headed several research domains in the area of high-level and system synthesis techniques and architectural methodologies, all within the Design Technology for Integrated Information and Telecom Systems (DESICS - formerly VSDM) division at the Inter-university Micro-Electronics Center (IMEC), Heverlee, Belgium. He is assistant professor at the EE department of the K.U.Leuven since 1989, and full professor (part-time) since 2000.

His current research activities belong to the field of architecture design methods and system-level exploration for power and area, mainly oriented towards memory management and global data transfer optimization. The major target application domains are real-time signal and data processing algorithms in image, video and end-user telecom applications, and data-structure-dominated modules in telecom networks. Both customized architectures and programmable (parallel) multimedia processors are targeted. In 1986 he received the Young Scientist Award from the Marconi International Fellowship Council. He was an associate editor for the "IEEE Transactions on VLSI Systems" for the period 1995/1998. Since 1999 he is an associate editor or the "IEEE Transactions on Multi-Media" and since 1996 an editor for Kluwer's "Journal of VLSI Signal Processing". Begin 1997 he became member of the steering board for the VLSI Technical Committee of the IEEE Circuits & Systems Society and since 1999 he also serves on the IEEE Trans. on VLSI Systems steering board. He was the program chair of the 1997 IEEE Intnl. Symposium on System Synthesis (ISSS) and the general chair for the 1998 ISSS. He will also be program chair of the 2001 IEEE Signal Processing Systems (SIPS) conference.

Reiner Hartenstein

Dr.-Ing. Reiner W. Hartenstein currently is professor of Computer Science and Engineering at Kaiserslautern University. He received all his academic degrees are from the EE Department at Karlsruhe University, where he later became Associate Professor of Computer Science.

Before joining Kaiserslautern he has worked in character recognition, image processing, digital and hybrid circuits and systems, and computer architecture. Since about ten years Prof. Hartenstein and his group works on reconfigurable computing and related compilation techniques. Supported by various funding agencies the achievements of his group are the definition and implementation of the high level hardware design languages KARL (textual) and ABL (graphic), the Xputer machine paradigm, the KressArray family (a reconfigurable generalization of the systolic array), and partitioning co-compilation for configware/software co-design.

Prof. Hartenstein, FPL fellow and Senior Member of the IEEE, organized numerous international workshops and conferences as a program chair (10 times), and also as industrial chair and general chair. He is founder of the PATMOS int'l workshop series on low power VLSI design and a co-founder of EUROMICRO as well as of the German multi-university E.I.S.-project (VLSI-Design). Prof. Hartenstein has authored or co-authored 15 books and more than 350 papers.

Vijay K Madisetti

Vijay K. Madisetti is a professor at the School of Electrical & Computer Engineering at Georgia Tech, specializing in the areas of digital signal processing and computer engineering. He is also the CEO of Soft.Networks, LLC, a telecom technology services and products company, with design centers in Atlanta, USA and Bangalore, India.

Dr. Madisetti leads a large embedded software research program (with 60+ faculty) as part of the State of Georgia's 80M$ Yamacraw initiative (, and has authored several books, including "VLSI Digital Signal Processors" (IEEE Press, 1995, 400 pages) and is the co-editor of IEEE/CRC Press "Digital Signal Processing Handbook" (1999, 2040 pages).

He was recently awarded the 2001 Outstanding PhD Dissertation Advisor Award by Georgia Institute of Technology.

Keshab K. Parhi

Keshab K. Parhi is a Distinguished McKnight University Professor of the Dept. of Electrical and Computer Engineering at the Univ. of Minnesota, Minneapolis. Currently he is spending a leave at Broadcom Corporation in Irvine, California. Dr. Parhi's research interests have spanned the areas of VLSI architectures for digital signal and image processing, adaptive digital filters and equalizers, error control coders, cryptography architectures, high-level architecture transformations and synthesis, low-power digital systems, and computer arithmetic. He has published over 320 papers in these areas, authored the text book VLSI Digital Signal Processing Systems (Wiley, 1999) and coedited the reference book Digital Signal Processing for Multimedia Systems (Marcel Dekker, 1999). He has served on editorial boards of IEEE Trans. on CAS, CAS-II, SP, VLSI Systems and SP Letters. He has received numerous best paper awards including the most recent 2001 IEEE W.R.G. Baker prize paper award. He is a fellow of IEEE and the recipient of a Golden Jubilee medal from the IEEE Circuits and Systems Society in 1999.

Lionel Torres

Lionel TORRES obtained respectively his Master degree and his phd degree in 1993 and 1996 from the University of Montpellier in France. After the Phd from 1996 to 1997 he was in ATMEL company as IP core methodology engineer. Since 1998 he became Assistant Professor at the University of Montpellier II inside the LIRMM laboratory (Laboratory of computer sciences, Microelectronic and Robotics of Montpellier). His research topics concerns, rapid system prototyping, programmable embedded cores and image processing. He was involved in different major conferences as DATE, VLSI, DCIS, IWLA, FPL, FPGA, RSP, ASIC-SOC, SBCCI and is author or co-author of more than 50 papers.

Jasmin Oz

Dr. Jasmin Oz is currently a DSP Software applications and research engineer at the Motorola Semiconductors research and development center, Herzliyah, Israel. She specializes in channel coding algorithms and applications, including various aspects of simulation, parallel programming, optimization and definition and development of new hardware.

Dr. Oz brings to her current position and interests a rich experience in diverse fields of academic and industrial research and development, including a B.Sc. in biology (Dept. of Biology, Technion, 1988), an M.Sc. in quantum physics (Dept. of Physics, Technion, Israel, 1991), a Ph.D. in analytical models for wave propagation in random media (Dept. of Physical Electronics, Tel-Aviv University, 1996), and the development of algorithms and simulations for statistical parameter estimation ELTA Israeli Aircraft Industries, Israel. She has published scientific articles, conference papers and industrial research reports in various topics.

Fadi J. Kurdahi

Fadi J. Kurdahi received the Ph.D. degree in Computer Engineering from the University of Southern California, Los Angeles, CA in 1987. Since 1987, he has been with the Department of Electrical & Computer Engineering at the University of California, Irvine where he holds a full professorship in ECE and ICS. He is currently with Morpho Technologies, a startup company developing reconfigurable computing solutions for communication appliances.

His areas of interest are reconfigurable computing, high-level synthesis of digital circuits, VLSI systems design and layout, and design automation. He has served on program committees of ISSS, ED&TC, ISCAS, among others. Dr. Kurdahi was Associate Editor of IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 1993-1995. He was Program Chair of the 1999 International Symposium on System Synthesis (ISSS) and the general Chair of ISSS 2000. He received an NSF Research Initiation Award in 1989, two ACM/SIGDA fellowships in 1991 and 1992, three distinguished paper awards in 1986, 1992, and 1998, and an NSF Information Technology Research Award in 2000. He is a member of IEEE and ACM.

Paul Master

Paul Master is the Vice President of Technology at QuickSilver Technology. Mr. Master has over 15 years experience in managing high technology communications and computer programs incorporating reconfigurable computing, digital signal processing, protocols, and systems. He has worked for Boeing, ARGO Systems, Acer America, and in several start-up companies focusing on multimedia and wireless communications. While at Boeing, Mr. aster founded a new division to bring three revolutionary products to market. These products included a smart antenna interference reduction cellular product line; a reconfigurable computing high-speed protocol analyzer product line for the intranet and Internet; and a communications network test-bed to support the network definition and algorithm development for Teledesic's Internet in the Sky. Mr. Master specializes in telecommunications, ASIC design, high-speed hardware designs and embedded multiprocessor software designs.