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Designing Networks On Chip: solutions and challenges

Luca Benini

Interconnection network design is becoming one of the most critical issues in current SoC development flows. Commonly adopted architectures (such as shared busses), do not scale well as complexity and parallelism increases, therefore circuit designers and chip architects are actively investigating alternative and novel approaches for eliminating communication bottlenecks. The quest for higher communication performance, reliability and energy efficiency is determining a paradigm shift from a computation-centric to a communication-centric view of SoC architectures, centered on the concept of Network-on-Chip. In this talk, we survey various network-on-chip architectures in last-generation multiprocessors on a chip for DSP, multimedia, graphics and various embedded application domains. We critically analyze the state of the art to pinpoint open challenges and opportunities, and to provide general NoC design guidelines.


Luca Benini
Luca Benini

Luca Benini is an Associate Professor at the Department of Electrical Engineering and Computer Science (DEIS) of the Universty of Bologna. He received a Ph.D. degree in electrical engineering from Stanford University in 1997. He also holds visiting researcher positions at Stanford University and the Hewlett-Packard Laboratories, Palo Alto, CA.

Dr. Benini's research interests are in all aspects of computer-aided design of digital circuits, with special emphasis on low-power applications, and in the design of portable systems. On these topics he has published more than 150 papers in international journals and conferences. He is a member of the organizing commitee of the International Symposium on Low Power Design. He is a member of the technical program committee of several technical conferences, including the Design Automation Conference, International Symposium on Low Power Design, the Symposiom on Hardware-Software Codesign.