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A Reconfigurable Processor and Software Environment for High Performance Embedded Systems

Fabio Campi

Embedded systems must execute a variety of high performance real-time tasks, such as audio, image and video compression and decompression, radio and internet protocol stacks. High hardware design and mask production costs dictate the need to re-use an architectural platform for as many applications as possible: an appealing option is to exploit the ever-improving Field Programmable Gate Array technology combining the user-friendliness of a conventional general purpose processor with the flexibility and performance of configurable hardware. This presentation describes a "Very Long Instruction Word", Risc processor architecture that adds a minimal set of specialized function units in order to efficiently implement common DSP algorithms, and uses a run-time reconfigurable datapath implemented on an embedded FPGA device to support application-specific instructions. The main design decisions will be discussed, specifying how they were supported by performance analysis using a flexible software development tool chain providing compilation, performance simulation and debugging facilities. Using some common embedded computation kernels as benchmark, it will be shown how the features of the architecture can be exploited in order to dramatically improve execution time and energy consumption with respect to a ``standard'' RISC processor.


Fabio Campi
Fabio Campi

Fabio Campi received the five years Dr.Eng. degree in Microelectronics at the University of Bologna, Italy in 1999. In 1996 he received a grant as an exchange student at the Tampere University of Technology, Tampere, Finland. Since 1999 he has been working as a consultant of Central R&D, ST Microelectronics in Agrate Brianza, Italy for the application of innovative CAD CMOS design platforms on digital System-on-chip design. In the last two years, he has been co-lecturer for "Design of Electronic Systems" at University of Bologna and "Digital Electronics" at the University of Cesena, Italy. He is currently PhD student at the "Advanced Reasearch Center on Electronic Systems E.DeCastro, (ARCES)", Bologna. His main research interest are VLSI System on chip design and development of advanced architectures and algorithms for digital signal processing.