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Abstract

Hardware and Software Generation for Application-Specific Multiprocessor SoC

Prof Ahmed Jerraya

Modern system-on-chip (SoC) design shows a clear trend towards integration of multiple processor cores, the SOC System Driver section of the "International Technology Roadmap for Semiconductors" (http://public.itrs.net/) predicts that the number of processor cores will increase dramatically to match the processing demands of future applications. Typical multiprocessor SoC applications like network processors, multimedia hubs and base-band telecom circuits have particularly tight time-to-market and performance constraints which require a very efficient design cycle.

A multiprocessor on SoC is composed of four kinds of components: software tasks, processors executing software, specific hardware cores and a global on-chip communication network. The crucial issue when designing SoC is to include hardware and software elements that adapt these components to each other. Multiprocessor SoC are quite different from classic symmetrical multiprocessor architectures. This is mainly because the implementation of system communication is much more complicated since heterogeneous processors are involved and complex protocols and topologies are used for communication.

Component-based design provides primitives to build complex architectures from basic components allowing design-architects to reuse efficient custom solutions with best performances. This talk explores a high-level component-based methodology and design environment for application-specific multiprocessor SoC architectures. The design environment provides automatic HW-SW interface generation tools. In order to adapt generic components, the environment is able to synthesize hardware interfaces, device drivers, and operating systems that implement a high-level interconnect API. This approach, experimented over the design of a VDSL system, shows a drastic design time reduction without any significant efficiency loss in the final circuit.

Bio

Ahmed Jerraya
Ahmed Jerraya

Dr. Ahmed Amine Jerraya received the Engineer degree from the University of Tunis in 1980 and the D.E.A., "Docteur Ingénieur", and the "Docteur d'Etat" degrees from the University of Grenoble in 1981, 1983, and 1989 respectively, all in computer sciences.

In 1986, he held a full research position with the CNRS (Centre National de la Recherche Scientifique). From April 1990 to March 1991, he was a Member of the Scientific Staff at Nortel in Canada, working on linking system design tools and hardware design environments.

He is the General Chair of HLDVT'02 and Co-Program Chair of CASES'02. He served as General Chair for DATE 2001, ISSS'96 and General Co-Chair for CODES'99. He also served as Program Chair for ISSS'95, RSP'96 and Co-Program Chair of CODES'97.

He published more than 100 papers in International Conferences and Journals. He received the Best Paper Award at the 1994 ED&TC for his work on Hardware/Software Co-simulation. Dr. Jerraya is currently managing the System-Level Synthesis group of TIMA Laboratory and has the grade of Research Director within the CNRS.