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Compiler design for modern embedded processor architectures

Rainer Leupers

Programmable processors are among the major building blocks in today´s embedded SoC designs. In contrast to desktop systems, there is a huge variety of domain specific and even application specific architectures, including microcontrollers, DSPs, NPUs, and ASIPs. The irregular architectures and very high code quality demands of embedded processors create a need for new compiler techniques beyond classical Dragon Book compilation. On one hand, this concerns novel code optimization techniques that take the detailed target architectures into account in order to minimize the overhead of compiled code versus hand-written assembly. On the other hand, retargetable compilers are needed, capable of generating code for flexible architectures, so as to support processor architecture exploration.

This presentation gives an overview of today´s retargetable compiler and code optimization technology for embedded processors. Additionally, new research challenges in the areas of architecture exploration and compilation for recent architecture families like VLIWs and NPUs will be covered.


Rainer Leupers
Rainer Leupers

Rainer Leupers received the Diploma and Ph.D. degrees in Computer Science with honors from the University of Dortmund in 1992 and 1997, respectively. From 1993 to 2001 he was a member of the Embedded Systems research group at Dortmund. His research and teaching activities revolve around software development tools for embedded systems, with emphasis on efficient compilers. In 2002, Dr. Leupers joined the ISS institute at Aachen University of Technology as a professor for Software for Systems on Silicon. He authored three books and numerous technical articles on compilers for embedded systems, and he received Best Paper Awards at DATE 2000 and DAC 2002. Additionally, he has been heading the embedded software tools group at ICD (Dortmund) and he is a co-founder of LISATek Inc.