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System Level Specification for Platform FPGAs

Satnam Singh

Platform FPGAs typically contain one or more processors (soft or hard), many system buses, external memory interfaces and edicated hardware and system peripherals like UARTs. Consequently many of the design challenges faced by SoC implementors for ASICs are now also faced by platform FPGA developers. Many of the same solutions apply e.g. extensive use of cores and the abstraction of communication to help manage system interconnection. This presentation shows how system level specification and configuration can be achieved using advanced language based features like type classes in Haskell. This provides a systematic way to specify platforms and to experiment with alternative implementations for sub-block and to help abstractly model communication. We show the advantages of performing platform tailoring using well tested and existing frameworks over ad hoc special purpose scripts for connecting together top-level SoC components. Finally, we suggest how advanced features like reconfigurable components can be modelled in our system.


Satnam Singh
Satnam Singh

Satnam Singh works in the area of novel hardware description languages and reconfigurable computing. He completed his PhD in 2000 which showed how to represent many circuit analyses in a systematic way using a technique called non-standard interpretation. As a lecturer at the Electrical Engineering Department and then Computing Science Department of the University of Glasgow he lead research into describing and implementing dynamically reconfigurable systems for high speed Postscript rendering and software radio applications. In conjunction with Mary Sheeran and Koen Classen at Chalmers Technical University he developed the Lava HDL which has been used to create high performed floorplanned FPGA circuits. He is currently working on adapting Lava for system level design at Xilinx Labs.