International Symposium on System-on-Chip
SoC | 1999 | 2000 | 2001 | 2002 | 2003 | 2004 | 2005 | 2006 | 2007 | 2008 | 2009 | 2010 | 2011 | 2012 | 2013 | 2014 | 2015

General

Conference

Lodging / Travel


Valid XHTML 1.1

Valid CSS!

Abstract

Coarse-grain Reconfigurability for Multimedia SoC

Stamatis Vassiliadis

In embedded system design, we are witnessing a shift towards the utilization of programmable processor cores which are augmented with reconfigurable hardware structures. This shift is even leading to single chip designs which can incorporate both hardwired and reconfigurable hardware. In this light, the MOLEN processor was introduced to achieve this tight integration by only a single one-time architectural extension.

The main idea for the MOLEN processor is to utilize custom configured harware to improve embedded system computing by re-introducing microcode concepts. First, we identify piece(s) of code from an application (set) that when sped up will result in an overall speedup of the application. Subsequently, hardware implementations of such pieces of code are mapped to reconfigurable hardware by writing high-level VHDL code. After synthesis, two types of microcode are generated: reconfiguration microcode (controlling the setting of the reconfigurable hardware) and execution microcode (controlling the execution of the implementation mapped on the reconfigurable hardware). Both types of microcode are referred to as reconfigurable microcode. This approach allows frequently used microcode (by identifying similar microcode across implementations) to be permanently stored on-chip. Furthermore, a storage facility is provided to temporarily store non-frequently used microcode in order to diminish their loading times. In addition, we introduce only two new architectural instructions (set and execute) to point to reconfigurable microcode. I.e., the new instructions do not specify the operation that needs to be performed, instead by executing the reconfigurable microcode the needed setting of and execution on the reconfigurable hardware is being performed. An additional benefit lies in the fact that the set instruction (which initiates reconfiguration microcode) can be scheduled well ahead of the execute instruction (which initiates execution microcode) and thereby hiding the reconfiguration latency of the hardware. The MOLEN approach is generic in the sense that it can support any application (set) and can be utilized to extend any programmable processor family that is augmented with reconfigurable hardware.

This presentation shows the concepts of the MOLEN processor by highlighting an extension of the hardware/software co-design paradigm that utilizes reconfigurable microcode. Furthermore, we present how the MOLEN approach can exploit coarse-grain reconfigurability in order to diminish reconfiguration latencies.

Bio

Stamatis Vassiliadis

Stamatis Vassiliadis was born in Manolates, Samos, Greece. He is currently the chairperson of the computer engineering laboratory and a chair professor in the Electrical Engineering department in T.U.Delft (Delft University of Technology), The Netherlands. He has also served in the faculties of EE of the Cornell University, Ithaca, NY and the State University of New York (S.U.N.Y.), Binghamton, NY. He worked for a decade with IBM in the Advanced Workstations and Systems laboratory in Austin TX, the Mid-Hudson Valley laboratory in Poughkeepsie NY and the Glendale laboratory in Endicott NY. In IBM he has been involved in a number of projects regarding computer design, organizations, and architectures and the leadership to advanced research projects. He has been involved in the design and implementation of several computer systems from mainframes to embedded. Examples of commercially available systems and processors that he personally worked on or that they use his inventions include the following: IBM 9370 model 60, IBM POWER II, IBM AS/400 Models 400, 500, and 510, IBM AS/400 Server Models 40S and 50S, IBM AS/400 Advanced 36, IBM S/390 Parallel Enterprise Server G4, MWAVE 3780i DSP, IBM S/390 Parallel Enterprise Server G5, IBM S/390 Parallel Enterprise Server G6, several Motorola/Apple/IBM processors including the 603e, 604e, 750..., the Motorola/Apple/IBM ALTIVEC, IBM Server z2000, BOPS ManArray, ...

For his work he received numerous awards including 24 levels of Publication Achievement Awards, 15 levels of Invention Achievement Awards and an Outstanding Innovation Award for Engineering/Scientific Hardware Design in 1989. Six of his patents have been rated with the highest patent ranking in IBM and in 1990 he was awarded the highest number of patents in IBM. While in IBM he was awarded 70 USA patents ranking him as the top all time IBM inventor. Dr. Vassiliadis received several paper awards including:

  • 2001 IEEE ICCD conference best paper award for the paper "MPEG Macroblock Parsing and Pel Reconstruction on an FPGA-augmented TriMedia Processor"
  • 1998 IEEE CAS conference best paper award for the paper "A Versatile Threshold Logic Gate"
  • 1992 ACM-IEEE Micro 25 conference honorable mention best paper award for the paper "Interlock Collapsing ALU for Increasing Instruction level

Dr. Vassiliadis has guided award winning PhD dissertations including the following:

  • 1992/1993 academic year: Candidate for Graduate Student Award For Excellence in Ph.D. Research (E.E. Dept. SUNY). Phd student: G. Triantafyllos
  • 1991/92 academic year: Distinguished Ph.D. Dissertation Award in Science, Mathematics, and Engineering (SUNY). Phd student: G. G. Pechanek. The first and the only best Ph.D. dissertation award ever awarded to an Electrical Engineering Ph.D. student at SUNY
  • 1990/1991 academic year: Graduate Student Award For Excellence in Ph.D. Research (SUNY). Phd student: G. G. Pechanek

Dr. Vassiliadis is a member of the IEEE Computer Society and an IEEE fellow.