International Symposium on System-on-Chip
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Block 1: Technology

[Steve Wilton] 09:00 Introduction to Reconfigurable Computing
Steve Wilton Associate Professor, University of British Columbia, CA

General introduction to reconfigurable computing technology.
Fine-grained and coarse-grained architectures.
Routing architectures.
Memory architectures for reconfigurable fabrics.
Embedded processors.

[Wayne Luk] 10:00 Techniques and tools for customising reconfigurable processors
Wayne Luk, Governors' Lecturer, Imperial College, UK

Summary of techniques and tools for customising reconfigurable processors.
Exploitation of domain-specific information.
Declarative and imperative program compilation.
Design-time and run-time customisation.
Customisation of data processors and instruction processors.
Customisable design tool frameworks and design platforms.

[Jeroen Leijten] 11:00 Design-time customisation and generation of reconfigurable processors
Jeroen Leijten, Co-founder, Chief Processor Architect, Silicon Hive, NL

Pre-fabrication application-domain-tuning of coarse-grained reconfigurable processors.
Template-based processor instantiation.
Data-path tuning for specific application domains.
Attaining extreme performance and low-power with data-paths that support single-cycle loops.
Application-domain-tuning for cost-sensitive scenarios.
Live demonstration, including the design and instantiation of a reconfigurable processor.

12:00 Lunch

Block 2: Applications mapping

[Lex Augusteijn] 13:00 Block-based mapping
Lex Augusteijn, Chief Compiler Architect, Silicon Hive, NL

The application mapping problem for lower data-rate applications.
Block-based computations with framed data in memory.
Application specification in high-level languages.
Compilers versus synthesis tools: Spatial compilation.
Techniques for automatically extracting intrinsic parallelism.
Live demonstration, compiling an FFT onto a highly parallel reconfigurable processor.

[Jos Huisken] 14:00 Stream-based mapping
Jos Huisken, Chief Silicon Designer, Silicon Hive, NL

The application mapping problem for higher data-rate applications.
Stream-based computations and data-flow-oriented DSP systems.
Application partitioning across reconfigurable cells.
Communication and synchronisation issues.
Using libraries of application macros and building systems.
Live demonstration, programming a QPSK satellite demodulator system onto a reconfigurable platform.

Block 3: System-level Issues

[Ernest] 15:00 Reconfigurable Communications Architecture for Adaptive Radios
Ernest Tsui, Principal Engineer, Corporate Technology Labs, Intel Corporation, USA

Adaptive radios, as opposed to fixed function radios, are necessitated by the proliferation of multitude of wireless connectivity protocols that will increasingly coexist and cooperate in multi-band multi-spectrum environments where compute/communication devices operate. An added impetus for the development of adaptive radios is underlined by the movement of regulatory bodies towards policy-based radios for efficient spectrum utilization. We motivate a solution for an adaptive radio architecture through the Reconfigurable Communications Architecture (RCA) that aims to provide ubiquitous network access via multiple Wireless LAN, PAN and WAN standards to users with personal computers, personal digital assistants and cell phones. RCA defines an infrastructure comprising a heterogeneous array of flexible accelerators, data-driven control and a mesh network for providing physical layer (PHY) and lower MAC processing. With the capability of being reconfigured for different standards, power and area approaching that of dedicated hardware, the capability of scaling to support future standards, and high-level programming tools for quick time to market, RCA is an attractive alternative to current methods of implementing PHY processing functions such as DSPs and ASICs.

[Vladimir] 16:00 Software Development Environment for Reconfigurable Communications Architecture
Vladimir Ivanov,Corporate Technology Group, Intel Corporation

We survey the software development environment for the Reconfigurable Communications Architecture (RCA). An RCA architecture overview from a software development point of view is presented. We motivate the specificities of the software development tools suite for this architecture necessitated by its massive-parallel form and reconfigurable processor elements (PE). The form of the architecture and its constituent functional elements defines the composition of its tools suite and its functional content. Programming flow for RCA is discussed. We provide a list of software development tools and consider a representative programming flow for the reconfigurable PEs. We discuss the complexities of the compiler and simulator developed for the RCA in the context of a generalized tools development concept.