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Tutorial on Nov. 15, 2004

Preliminary programme.

Engineering Complex SOCs

Tutorial Outline:

  • 1. The SOC design problem
  • 2. System design and MP-centric design
  • 3. Application acceleration
  • 4. Configurable processor basics
  • 5. Hardware alternatives for complex SOC design
  • 6. Energy-efficient SOC design
  • 7. The future of SOC design


  • Dr. Chris Rowen, President and CEO, Tensilica, Inc., Santa Clara, CA
  • Prof. Dr. Norbert Wehn, University of Kaiserslautern, Kaiserslautern, Germany
  • Max Baron, Senior Editor & Principal Analyst, MicroDesign Resources, San Jose, CA
  • Steven Leibson, Tensilica, Inc., Santa Clara, CA

Tutorial Description:

This 1-day tutorial is based on Dr. Chris Rowen’s recently published book, “Engineering the Complex SOC” (Prentice Hall, 2004). The tutorial is aimed at architects and designers involved with complex SOC design who need to understand how to develop complex, mega-gate SOCs under severe time and cost constraints. Managers of companies making significant investments in SOC designs and platforms will also find the information in this tutorial essential to making decisions regarding the changes they may need to make in investment strategies, core competencies, and organization structure over time.

The tutorial outlines the major forces changing today’s SOC design process, and introduces the concept of SOC design using extensible processors as a basic design fabric. It teaches the essentials of extensible processor architecture, tools for instruction-set extension, and multiple-processor SOC architecture for embedded systems. It uses examples from Tensilica’s Xtensa architecture and the Tensilica Instruction Extension (TIE) language throughout to give a precise, practical, and up-to-date picture of the real issues and opportunities associated with this new design method.

Note: The first 100 people to sign up for this tutorial will receive a free copy of “Engineering the Complex SOC,” in addition to the materials prepared for this 1-day course.

Section Descriptions:

Section 1 of the tutorial provides a high-level introduction to the many SOC design problems and their solutions. The middle sections give a more detailed look at how extensible processors compare to both traditional processors and hardwired logic. Also covered are the essential mechanisms of processor extensibility that address both the computation and communication needs of advanced SOC architectures. The later sections give a series of detailed examples to reinforce the applicability of the new SOC design method.

Section 2 provides a current view of SOC hardware structure, software organization, and chip-development flow. This section exposes the six basic shortcomings of the current SOC design method and the reasons why new structures and processes are necessary.

Section 3 takes a top-down approach to application acceleration using a processor-centric SOC design approach, looking at overall data flow through complex system architectures. This section shows how complex functions are decomposed into function blocks which may often be implemented as application-specific processors. Key issues include latency and throughput of blocks, programming models for coordination of parallel functions, hardware interconnect options, and management of complexity across the entire chip design. This section contains a case study using the processor-centric design approach to implement channel-coding algorithms for cellular telephony.

Section 4 looks at task design through the eyes of the hardware developer, especially at the process of translating hardware functions into application-specific processors with comparable performance but with the added benefit of complete programmability. This section establishes the basic correspondence between hardware pipelines and processor pipelines and recommends techniques for efficient mapping of traditional hardware functions (including high-bandwidth, low-latency functions) into application-specific processors.

Section 5 deals with a series of more advanced SOC-design topics and issues, including techniques for implementing complex state machines, options for task-to-task communication and synchronization, interfaces between processors and remaining hardware blocks, power optimization, and details of the Tensilica Instruction Extension language.

Section 6 deals with the power-dissipation issues present in the design of any complex SOC and gives recommendations for reducing power dissipation in processor-centric SOC designs.

Section 7 looks down the road at the longer-term future of SOC design, examining basic trends in design methodology and semiconductor technology. It paints a 10-15 year outlook for the qualitative and quantitative changes in design, in applications, and in the structure of the electronics industry.