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Panel discussion: The Power Wall - how to get over, through, or around?

SoC 2007 Tampere hall


  • Mika Kuulusa (MK)
  • Dennis Sylvester (DS)
  • Gert Goossens (GG)
  • Raj Nair (RN)
  • Tobias Noll (TN)
  • Petri Solanti (PS)
  • chair Jari Nurmi (JN)


Opening of the discussion by JN: Are we meeting the power wall now?
TN: It depends on the application and the used CPU. Today, the area is still concern number one, power consumption is not so important.
RN: The power wall might appear to be rubber one, it could be bent. The battery technology must be improved. In addition, portable devices cannot be hot potatoes because they are hand-held.
MK: Nowadays the mobile phones are portable computers already. More performance is needed constantly.
DS: We are talking a little bit less of a wall, instead it could be seen as a set of hurdles. Some hurdles are already passed (e.g. power gating) but also the functionality has already been limited by the power budget.
JN: More or less we are already leaning the wall.
PS: Power efficiency has improved a lot in mobile phones. The packing density is growing and causing thermal problems. We are talking about a compromise between heat, power, and performance.
Questions from the audience:
Q: Could the energy be produced in the component itself e.g. in the mobile phones? Is there any research in another ways of charging the devices other than plugging the devices into the wall?
MK: About the fuel cell, fundamental problem is the fuel. When using fuel in a mobile device it gets very complicated. However, a standard plug for the charger of all mobile phones could be one helping point.
JN: How about the solar cells?
MK: They do not work in Finland because of little sun shine. The hand-held devices must look nice and cool and solar cells would ruin that.
GG: Energy scavenging methods in wireless sensor networks, getting energy from the body heat and moving parts near the device are under research.
DS: The secondary power sources e.g. obtaining the energy from vibrations is in microwatt level which is not enough. We could implement hybrid energy sources i.e. two types of batteries in one device so if another runs out there is still some energy left from the other source.
JN: How about the wireless power transfer? Will we see that soon?
DS: Actually, there has been some break-thru in that area. A small amount of energy has been successfully transferred wirelessly a short range. In wireless power transfer there are some environmental questions to be considered, too.
Back to business:
Q: About the power wall, we have gone through a number of obstacles during the past e.g. mask distortion to scale the distances. Is the power wall just a hurdle or are we stopping now?
GG: Throughout the years people have always been pushing the limits. The static power consumption becomes more important but it is still just another hurdle.
DS: Any of these obstacles has not been deadly. Despite the power wall still some things work. The power consumption can always be lowered e.g. by lowering the voltage. However, a lot of innovations are still needed.
PS: There are two aspects that have not been discussed today: interconnect structure and SW efficiency. The most common interconnect is still a bus. New types of memory architectures and interconnects are needed to enable more parallel processing to decrease the power consumption. The SW quality needs to be improved to efficiently use new kinds of memory and interconnect architectures.
JN: Do SW developers know anything about the power consumption?
PS: They know very little. The SW developers mainly consider things e.g. how to efficiently index a table in the memory. The power awareness needs to be improved.
MK: The SW coders are mainly considering how the web pages look and the application functionality rather than the power consumption, unless it is explicitly specified.
GG: When we are talking about power consumption, deeply embedded SW and application SW must be separated. From application SW there is a significant amount of code ported straight from PC (x86) code. The power consumption has not been thought at all. There is a lot that can be gained in this area. The industry companies should provide tools for power aware SW development.
PS: I do not agree with GG. A cache miss is a cache miss despite the application context.
TN: There could be a technique developed for the power estimation for SW code. It would take as input a piece of code and a model for CPU. However, the need has not been high enough for these kinds of tools.
PS: Actually, a couple of years ago there was a power tool introduced for the SW community. The company disappeared because there was no need for this kind of tool back then.
Comment (C): About the memory architectures. The memories e.g. SRAM are power hungry. Should we be focusing on more energy efficient memories (e.g. MRAM)? Are there any techniques to reduce memory power overhead?
DS: That is not a problem because having more than a few megabytes of memory is very rare in mobile devices. If the overall cost of the device is very low there is nothing to be done with a few exotic techniques in order to optimize the memory power consumption.
C: The memories are not sparse. I agree to that.
DS: We care more about the power than the area. Embedded flash memories cost much for a fabless company.
C: I agree also to that. Are not the mobile phone markets the driving force?
MK: The dynamic power consumption is not a problem in SRAMs but the leakage power is. The main memory round-trip time and latency kills energywise.
RN: MRAMs have still problems with power. However, MRAMs can definitely be applied to some applications. There is more hope for more dense memory technology than MRAMs, programmable metallization, and operating at very low voltages.
Yet another question:
Q: When some part of chip is turned on, it should be kept busy as much as possible for the power and when it is not needed anymore, it should be turned off. Opinion on how this affects the chip designers?
RN: The keynote pointed out that if you want to cope with power you should think of whole new techniques. The processing units should be kept simpler. In addition, running the application is more predictable with simpler processing units.
DS: We have already seen evidence about simplicity. Intel moved away from the huge pipeline in Pentium 4 to a uses a shorter one in the new processors. The overall trend is towards many simpler cores instead of a single complex one.
MK: Also the scalability range is huge in applications.
Q: If we think of many simpler processing units. Will the interconnect energy consumption be a problem and is the interconnect going to be a bottleneck and how far is it?
TN: The behavior of interconnect becomes important. The interconnects should be kept as local as possible.
DS: 3D-integration leads to shorter wires. There is a lot of potential in that aspect. It is an obvious win from the implementation point of view. Only cost is an issue.
PS: The interconnect problem has been under research by some companies. I still have not seen an intelligent way for short wires. It is an architectural question. Maybe some sophisticated logic could be used to bypass some nodes. Many people want to keep Amba bus and some particular core in their implementations despite of a bunch of new possibilities. The architecture should be revisited.
JN: Do you mean NoC?
GG: NoC is for general purpose computing paradigm. We have to go application specific architectures. The computing must become local.
PS: Considering shared memory and the DMA transfers related to it. In many cases those could be replaced by a FIFO.
MK: NoC should be skipped totally. It is not a new term anymore.
Adding some heat:
Q: Multimedia and image processing is very regular from application point of view. Algorithmic level tasks should be separated to complex and simple operations for power point of view and divided to different processing units. 3D-integration is very attractive but it does not solve the heat issue?
DS: In 3D architectures removing the heat is very challenging. Microfluidics could be applied but it does not solve the issue yet. A more realistic scenario would be voltage lowering. More HW accelerators should be used for power efficient computing. Moreover, the computation could be performed so that the result is not always correct but it is correct with some probability. By doing so the safe margins in design process could be smaller. In some applications small amount of errors does not matter.
PS: About scaling the computing power and scheduling the instructions to different processing units. Superscalar architectures do it in HW and the most power goes to scheduling. In VLIW architectures the compiler decides the processing which leads to less power consumed during the execution. There is a new wall for the compiler developers.
MK: In mobile phones the common dominator is ARM CPU. In addition, everybody has to have their own DSP. Let us take Nokia N95 mobile phone as an example: 200 mm2 silicon. When a user just browses through the internet and does some fun stuff there is so much wasted silicon unless the user decides to play a 3D game. N95 has 5-6 ARMs in addition with some other processing elements. There are lots of clock cycles wasted in a common use case.
PS: Why there has to be so many ARMs? Why not to combine several cores to one core?
GG: The ARMs are not all in one chip. For instance, Bluetooth utilizes its own ARM. In addition, not all phones are massive multimedia phones alike N95 so less cores can be used.
MK: Basically for Bluetooth, the integrators do not care what handles its processing.
PS: Intel is the only one processor provider in the PC world in addition with AMD. ARM seems to be the CPU in the mobile world. Why nobody is looking for better alternatives?
GG: Usually, it is the matter of legacy (code).
PS: Why legacy is so important?
GG: Recompiling protocol stack for new alternatives is the obstacle.

The final steps:

MK gave a short presentation on how Nokia is taking the power consumption seriously already. He presented a tool developed in Nokia called Energy Profiler. It can measure the used current and power consumption in a phone in real time. The motivation for developing the tool was the 3W power barrier.

JN concluded the whole panel discussion by saying that the power density is a big hurdle but not a big wall.