International Symposium on System-on-Chip
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Technical Programme

The advanced programme is below.

Monday Nov. 19

Session MonAm1: Tutorial
 Time:  09:00 - 17:00
 Location: Sonaatti

                   Tutorial on Processor Design (see "Tutorial")

Session MonPm1: ESCUG
 Time:  17:00 - 21:00  
 Location: Sonaatti

                   European SystemC Users' Group Meeting

Tuesday Nov. 20


SESSION TueAm1: Opening
 Time: 10:00 - 10:15
 Location: Studio

SESSION TueAm2: Keynote
 Time: 10:15 - 11:00
 Location: Studio

 10:15   	  [1053] SCALING THE POWER WALL - KEYNOTE SPEECH
                  Jan Rabaey, UC Berkeley, USA

SESSION TueAm3: Industry1 and Coffee
 Time: 11:00 - 12:00
 Location: Rondo

 11:00            FPGA: Fast Prototypes are Great for ASIC
                  Doug Amos, Synplicity, UK; Antti Innamaa, Synplicity, Finland   

 11:30            Practical GALS for Multicore Systems   
                  Steve Hamilton, Sonics, USA       

SESSION TueAm4: Invited2
 Time: 12:00 - 12:45
 Location: Studio

 12:00   	  [1051] - EMBEDDED PROCESSOR DESIGN FOR LOW POWER CONSUMPTION
                  Kristzian Flautner, ARM, UK
 
SESSION TueLunch: Lunch
 Time: 12:45 - 14:00
 Location: Restaurant Fuuga

SESSION TuePm1: Invited3
 Time: 14:00 - 14:45
 Location: Studio

 14:00   	  [1050] - LOW-POWER ARITMETICS FOR SOC
                  Tobias Noll, RWTH Aachen, Germany


SESSION TuePm2: Industry2
 Date: November 20, 2007
 Time: 14:45 - 15:45
 Location: Rondo

 14:45   	 [1023] - DEVELOPMENT OF COMPLEX SOC DEVICES REQUIRE NEW DESIGN TECHNOLOGIES
                          Guido Schreiner, The MathWorks, Germany
 
 15:15  	 [1047] - RENDEZVOUS-BASED MOC FOR UNTIMED TLM
                          Rohit Jindal, ST Microelectronics, India;
			  Laurent Maillet Contoz, ST Microelectronics, France

SESSION TuePm3: Poster1 and Coffee
 Time: 14:45 - 15:45
 Location: Rondo

	 [1025] - IMPLEMENTING THE CONJUGATE GRADIENT ALGORITHM ON MULTI-CORE SYSTEMS
	                Wouter Wiggers, Vincent Bakker, Andre Kokkeler, Gerard Smit,
	                University of Twente, Netherlands
 
	 [1026] - A NOVEL EMULATION TECHNIQUE THAT PRESERVES CIRCUIT STRUCTURE AND TIMING
                        Leos Kafka, Martin Danek, UTIA AS CR, Czech Republic;
			Ondrej Novak, CTU in Prague, Czech Republic
 
	 [1031] - A NEW LMMSE RECEIVER ARCHITECTURE WITH DYNAMIC FILTER LENGTH OPTIMISATION
	                Mark Tennant, Ahmet Erdogan, Tughrul Arslan, John Thompson,
	                University of Edinburgh, United Kingdom
 
	 [1003] - A SYSTEM-LEVEL DESIGN METHOD FOR COGNITIVE RADIO ON A RECONFIGURABLE
	               MULTI-PROCESSOR ARCHITECTURE
	               Qiwei Zhang, Andre B.J. Kokkeler, Gerard J.M. Smit,
		       University of Twente, Netherlands
 
	 [1018] - A REAL-TIME LEARNING PROCESSOR BASED ON K-MEANS ALGORITHM WITH 
                  AUTOMATIC SEEDS GENERATION
	               Hirotsugu Shikano, Kiyoto Ito, Kazuhide Fujita, Tadashi Shibata,
		       The University of Tokyo, Japan
 
SESSION TuePm4: Sensing and Image Processing SoC
 Time: 15:45 - 17:05
 Location: Studio

 15:45  	 [1015] - MIXED-SIGNAL FOCAL-PLANE IMAGE PROCESSOR EMPLOYING TIME-DOMAIN
                 COMPUTATION ARCHITECTURE
                 Kiyoto Ito, Tadashi Shibata, The University of Tokyo, Japan
 
 16:05  	 [1033] - INTELLIGENT CAMERAS AND EMBEDDED RECONFIGURABLE COMPUTING:
                 A CASE STUDY ON MOTION DETECTION
                 Claudio Mucci, Luca Vanzolini, Antonio Deledda,
		 ARCES - University of Bologna, Italy; Fabio Campi, STMicroelectronics,
		 Italy; Gerard Gaillat, THALES Optronique S.A., France
 
 16:25  	 [1038] - A FEATURE-BASED OPTICAL FLOW PROCESSOR ARCHITECTURE FEATURING
                 SINGLE-MOTION-VECTOR/CYCLE GENERATION
                 Kazuhide Fujita, Kiyoto Ito, Tadashi Shibata,
		 The University of Tokyo, Japan
 
 16:45  	 [1044] - SENSOR NETWORK-ON-CHIP
                 Girish Varatkar, Sriram Narayanan, Naresh Shanbhag, Douglas Jones, 
		 University of Illinois at Urbana Champaign, United States
 
SESSION TuePm5: SoC Design Methodology
 Time: 15:45 - 17:05
 Location: Rondo

 15:45  	 [1006] - THE BULK BUILT IN CURRENT SENSOR APPROACH FOR SINGLE EVENT
                 TRANSIENT DETECTION
                 Gilson Wirth, UFRGS, Brazil; Christian Fayomi, 
		 Universite du Quebec a Montreal, Canada
 
 16:05  	 [1007] - A CONFIGURATION LOCKING TECHNIQUE TO REDUCE THE CONFIGURATION
                 OVERHEAD OF RUN-TIME RECONFIGURABLE DEVICES
                 Yang Qu, Juha-Pekka Soininen, Technical Research Centre of Finland (VTT),
		 Finland; Jari Nurmi, Tampere University of Technology, Finland
 
 16:25  	 [1017] - HEURISTICS FOR SCENARIO CREATION TO ENABLE GENERAL LOOP
                 TRANSFORMATIONS
                 Martin Palkovic, Imec, Belgium; Henk Corporaal, TU Eindhoven,
		 Netherlands; Francky Catthoor, Imec, Belgium
 
 16:45  	 [1020] - OPTIMAL SUBSET MAPPING AND CONVERGENCE EVALUATION OF MAPPING
                 ALGORITHMS FOR DISTRIBUTING TASK GRAPHS ON MULTIPROCESSOR SOC
                 Heikki Orsila, Erno Salminen, Marko Hännikäinen, Timo Hämäläinen, 
		 Tampere University of Technology, Finland
 
SESSION TueHockey: Ice Hockey Ilves vs. HIFK
 Time: 18:30 - 21:00
 Location: Hakametsä Ice Hall
 Sponsor(s): Mentor Graphics

SESSION TueDinner: Simple Supper
 Time: 21:00 - 23:00
 Location: Restaurant Plevna

Wednesday Nov. 21


SESSION WedAm1: Invited4
 Time: 09:00 - 09:45
 Location: Studio

 09:00   	  [1048] - LOW-POWER RF DESIGN FOR SOC
                  Kavé Kianush, Catena Radio Design B.V., The Netherlands
 
SESSION WedAm2: Industry3
 Time: 09:45 - 10:45
 Location: Rondo

 09:45   	  [1055] - IMPLEMENTING FLEXIBLE INDUSTRIAL ETHERNET IN FPGA
                  Bob Blake, Altera, UK

 10:15            [1012] - REDUCE SOC ENERGY CONSUMPTION THROUGH ISA EXTENSION
                  Steven Leibson, Tensilica, United States

SESSION WedAm3: Poster2 and Coffee
 Time: 09:45 - 10:45
 Location: Rondo

	 [1036] - MAPPING STREAMING APPLICATIONS ON A RECONFIGURABLE MPSOC PLATFORM
                  AT RUN-TIME
                  Philip Hölzenspies, Gerard Smit, Jan Kuper, University of Twente, Netherlands
 
	 [1040] - MANAGING RECONFIGURABLE RESOURCES IN HETEROGENEOUS CORES USING
                  PORTABLE PRE-SYNTHESIZED TEMPLATES
                  Marco Domenico Santambrogio, Matteo Giani, Politecnico di Milano, Italy;
                  Seda Ogrenci Memik, Northwestern University, United States
 
	 [1045] - POWER MANAGEMENT AND CLOCK GENERATOR FOR A NOVEL PASSIVE UWB TAG
                  Majid Baghaei-Nejad, Hannu Tenhunen, Li-Rong Zheng, KTH, Sweden
 
	 [1005] - MANAGING CONCURRENCY BY SUPPORTING OBJECT-ORIENTED PROGRAMMING WITH
                  HYBRID DATA-DRIVEN CONTROL-FLOW PROCESSOR
                  Raimo Mäkelä, Olli Vainio, Tampere University of Technology, Finland
 
	 [1010] - RUN-TIME SCHEDULED HARDWARE ACCELERATION OF MPEG-4 VIDEO DECODING
                  Jani Boutellier, University of Oulu, Finland; Pekka Jääskeläinen, 
                  Tampere University of Technology, Finland; Olli Silvén,
                  University of Oulu, Finland
 
	 [1011] - CONFIGURABLE HARDWARE/SOFTWARE SUPPORT FOR SINGLE PROCESSOR REAL-TIME
                  KERNELS
                  Susanna Nordstrom, Lars Asplund, Malardalen University, Sweden
 
	 [1022] - FPGA PROTOTYPE OF THE REALJAVA CO-PROCESSOR
                  Tero Säntti, Joonas Tyystjärvi, University of Turku, Finland; 
                  Juha Plosila, Academy of Finland, Finland
 
SESSION WedAm4: Modelling and Analysis
 Time: 10:45 - 11:45
 Location: Studio

 10:45  	 [1004] - CMOS IC DESIGN AND VERILOG-A MODELLING OF 10-GB/S PLL-BASED
                 DESERIALIZER FOR INTER-CHIP COMMUNICATION IN SOC
                 Maher Assaad, David Cumming, University of Glasgow, United Kingdom
 
 11:05  	 [1008] - ALGORITHM FOR FAST STATISTICAL TIMING ANALYSIS
                 Jakob Salzmann, Frank Sill, Dirk Timmermann, University of Rostock,
                 Germany
 
 11:25  	 [1034] - MIGRA: A TASK MIGRATION ALGORITHM FOR REDUCING TEMPERATURE
                 GRADIENT IN MULTIPROCESSOR SYSTEMS ON CHIP
                 Salvatore Carta, University of Cagliari, Italy; Andrea Acquaviva, 
		 University of Verona, Italy; Fabio Mereu, University of Cagliari, 
		 Italy; Giovanni De Micheli, Ecole Politechnique Federale de Lausanne, 
		 Switzerland
 
SESSION WedAm5: Processor Architectures
 Time: 10:45 - 11:45
 Location: Rondo

 10:45   	 [1056] - MULTI-ASIP SOCS - OR HOW TO DESIGN ULTRA-LOW POWER
                 ARCHITECTURES FOR WIRELESS AND MULTI-MEDIA SYSTEMS
                 Gert Goossens, Target Compiler Technologies, Belgium
 
 11:05  	 [1016] - THE NOCRAY GRAPHIC ACCELERATOR: A CASE-STUDY FOR MP-SOC
                 NETWORK-ON-CHIP DESIGN METHODOLOGY
                 Sergio Tota, Mario Casu, Paolo Motto, Massimo Ruo Roch, 
		 Maurizio Zamboni, Politecnico di Torino, Italy
 
 11:25  	 [1028] - CONTROL AND DATAPATH DECOUPLING IN THE DESIGN OF A NOC SWITCH:
                 AREA, POWER AND PERFORMANCE IMPLICATIONS
                 Davide Bertozzi, Simone Medardoni, University of Ferrara, Italy; 
		 Luca Benini, University of Bologna, Italy; Enrico Macii, 
		 Politecnico di Torino, Italy
 
SESSION WedAm6: Invited5
 Time: 11:45 - 12:30
 Location: Studio

 11:45   	 [1054] - IS YOUR LOW-POWER DESIGN SWITCHED ON?
                 Mark Croft, Mentor Graphics, UK

SESSION WedLunch: Lunch
 Time: 12:30 - 13:45
 Location: Restaurant Fuuga

SESSION WedPm1: Invited6
 Time: 13:45 - 14:30
 Location: Studio

 13:45   	 [1052] - POWER DELIVERY, INTEGRITY ANALYSIS, AND MANAGEMENT
                 IN NANOSCALE SOC/SIP, Raj Nair, ComLSI, USA
 
SESSION WedPm2: Industry4 and Coffee
 Time: 14:30 - 15:30
 Location: Rondo

14:30   	 POWER ANALYSIS FOR SOFTWARE DEVELOPMENT
                 Petri Solanti, Synopsys, Finland

15:00		 DSP VALLEY
                 Peter Simkens, DSP Valley, Belgium

SESSION WedPm3: On-Chip Communication and Logic
 Time: 15:30 - 16:30
 Location: Studio

 15:30  	 [1019] - USING A LINEAR SECTIONED BUS AND A COMMUNICATION PROCESSOR TO
                 REDUCE ENERGY COSTS IN SYNCHRONOUS ON-CHIP COMMUNICATION
                 Kris Heyrman, University College Ghent, Belgium; Antonis Papanikolaou, 
		 IMEC, Belgium; Francky Catthoor, Katholieke Universiteit Leuven, 
		 Belgium; Peter Veelaert, University College Ghent, Belgium; 
		 Wilfried Philips, TELIN, Ghent University, Belgium
 
 15:50  	 [1035] - A NEW LOOK AT REVERSIBLE LOGIC IMPLEMENTATION OF DECIMAL ADDER
                 Rekha K. James, Shahana T. K., K. Poulose Jacob, 
                 Cochin University of Science and Technology, India; Sreela Sasi, 
		 Gannon University, United States
 
 16:10  	 [1039] - 3-GB/S, SINGLE-ENDED ADAPTIVE EQUALIZATION OF BIDIRECTIONAL
                 DATA OVER A MULTI-DROP BUS
                 Henrik Fredriksson, Christer Svensson, Linköping University, Sweden
 
SESSION WedPm5: Invited7
 Time: 16:30 - 17:15
 Location: Studio

 16:30   	[1049] - ENERGY-OPTIMAL CIRCUIT DESIGN
                Dennis Sylvester, University of Michigan, USA
 
SESSION WedPm6: Short break
 Time: 17:15 - 17:30
 Location: in front of Studio

SESSION WedPm7: Panel discussion: The Power Wall - how to get over, through, or around?
 Time: 17:30 - 18:30
 Location: Studio

SESSION WedDinner: Banquet in downtown Tampere
 Time: 19:00 - 22:00
 Location: Viking Restaurant Harald