Modern FPGA-based systems are complex and difficult to verify. One approach to easing the verification problem and reducing perceived complexity is to use libraries of reusable functions. These reusable functions, known as intellectual property blocks, are commonly created as netlists or RTL components. Complex systems can be created from IP blocks by using high-level design environments. These tools define the types and semantics of component interfaces which permit systems to be debugged using system-level transaction monitoring. However, the insertion of on-chip monitoring circuitry is a manual process in FPGA design flows. In this paper we will present an algorithm which exploits the high-level design environment to permit automatic instrumentation of designs. We will demonstrate that the algorithm can harness existing HDL generation techniques and reduce the insertion and configuration effort required of the designer.