Adaptive Circuit Block Model for Power Supply Noise Analysis of Low Power System-on-Chip

Matthias Eireiner1,  Paul Wallner2,  Andreas Schoene2,  Stephan Henzler2,  Ulrich Fiedler2,  Doris Schmitt-Landsiedel1
1Technical University Munich, 2Infineon Technologies AG, Munich


A circuit block model and methodology for accurate power supply noise analysis, taking the impact of power supply noise on the current consumption into account, is presented. This enables high transient accuracy even at excessive power supply noise. Further improvement is obtained by an adaptive model for the capacitance of switching gates. Simulation results for various power grids and test circuits show an increased accuracy of 4.7X - 20X, at a simulation run time penalty of roughly 20%. This makes it especially helpful for low power SoC designs, with high transient IR-Drop and multi-frequency domains, where transient accuracy is of concern.