Due to technology scaling, on-chip communication is an important bottleneck in the design of high performance Systems-on-Chip (SoC). Network-on-Chip (NoC) has been proposed as a possible solution to address the issues of communication in SoC. It is envisaged that in future deep sub-micron (DSM) technologies, device variability will shift the design paradigm from deterministic to probabilistic. Thus it becomes important to have a complete understanding of the impact the variability will have on the performance of future NoC designs in order to achieve high yield and reliable communication architectures. In this paper we undertake a first step towards the study of the impact random dopant fluctuation (RDF) in the devices will have on on-chip synchronous communication structures, such as line drivers, repeaters and latches. The study is based on Monte Carlo simulation of the circuits at the 25, 18 and 13 nm technology generations using predictive device models. FO4 delay has been measured and taken as a baseline for the given technologies to make a comparison of the speed and variability of the communication structures. It has been found that variability has a significant impact on the performance of communication structures designed using small devices. Therefore, as a design methodology, it is proposed to use larger sized devices in critical parts of the circuits at the cost of larger area and power. Surprisingly, this work also points out that tapered buffers with larger tapering factor are more prone to delay variability, which might lead into reconsidering the optimal sizing of these structures. It may very well be possible to tackle such variabilities with active approaches, which are beyond the scope of this text.