Two Phase Clocked Adiabatic Static CMOS Logic

Nazrul Anuar Nayan1,  Yasuhiro Takahashi2,  Toshikazu Sekine2
1Graduate School of Engineering, Gifu University, 2Gifu University


This paper presents a new quasi adiabatic logic family that uses two complementary split-level sinusoidal power supply clocks for digital low power applications such as sensors. The proposed two phase clocked adiabatic static CMOS logic (2PASCL) circuit utilizes the principle of adiabatic switching and energy recovery. It has a node switching activity that is lower than dynamic logic and can be directly derived from static CMOS circuits. By using SPICE, we simulate the inverter logic of 2PASCL implemented using 0.18 mu CMOS technology. A driving pulse with the height equal to V_{dd} is supplied to the gates. Compared with other proposed simple adiabatic logic inverters, 2PASCL shows the lowest in energy dissipation. As an application, we design and simulate a 4-bit ripple carry adder (RCA) using 2PASCL logic gates. From the simulation result, 2PASCL RCA can save an average of 71.3% of energy dissipation compared with static CMOS RCA logic at transition frequencies of 10 to 100 MHz.