Technology scaling into subnanometer range will create process variations which has impact on the overall manufacturing yield and quality. At the same time System-on-Chip (SoC) complexity and communication requirements are increasing which will make a SoC designer goal to design a fault-free system a very difficult task. The dependability will be an important measure of System-on-Chip design process. As a result we see a shift from bus based systems into networked systems and from traditional Register Transfer Level (RTL) design paradigm into higher abstraction levels – High Level Synthesis (HLS) and system-level design. In real-time networked systems the dependability cannot be reached effectively without predictable contention free communication synthesis. In this paper, an approach that takes into account flow control unit(s) transmission latencies over actual links, is extended to cover, in addition to virtual cut-through, also wormhole switching and wormhole switching with virtual channels. The communication synthesis results are used in our proposed system-level design methodology for dependable real-time Systems-on-Chip.