Flexible DOR Routing for Virtualization of Multicore Chips

Frank Olaf Sem-Jacobsen1,  Tor Skeie1,  Samuel Rodrigo2,  José Flich2,  Davide Bertozzi3,  Simone Medardoni3
1Networks and Distributed Systems, Simula Research Laboratory, Lysaker, Norway, 2Parallel Architectures Group, Technical University of Valencia, Valencia, Spain, 3ENDIF, Department of Engineering, University of Ferrara, Ferrara, Italy


The expected increase in number of cores on a single chip leads to the necessity of high-performance on chip interconnects (NoC). Furthermore, in order to fully utilize the abundance of cores, the chip is expected to support a number of applications running on the chip simultaneously. It is therefore necessary to partition the chip to support numerous applications without any risk of interference between them. The success of this depends on the flexibility of the underlying routing algorithm. This paper presents a flexible routing algorithm based on dimension ordered routing, which supports a large variety of irregular (2-D and 3-D) mesh topologies. The algorithm provides high efficiency at very low additional complexity, as is confirmed by experimental results.