A Multi-Core Signal Processor for Heterogeneous Reconfigurable Computing

Davide Rossi1,  Fabio Campi2,  Antonio Deledda1,  Claudio Mucci3,  Stefano Pucillo3,  Sean Whitty4,  Rolf Ernst4,  Stéphane Chevobbe5,  Stephane Guyetant5,  Matthias Kühnle6,  Michael Hübner6,  Jurgen Becker6,  Wolfram Putzke-Roeming7
1ARCES,University Of Bologna, Italy, 2ST Microelectronics, Agrate Brianza, Italy, 3STMicroelectronics, Agrate Brianza, Italy, 4Technische Universität Braunschweig, Germany, 5CEA, Paris, France, 6ITIV, University Of Karlsruhe, Germany, 7Thomson, Germany


Reconfigurable computing holds the promise of delivering ASIC-like performance while preserving run-time flexibility of processors. In many application domains, the use of FPGAs is limited by area, power, and timing overheads. Coarse-Grained Reconfigurable Architectures offer higher computation density, but at the price of rather being domain specific. Programmability is also a major issue related to all of the described solutions. This paper describes a heterogeneous multi-core system-on-chip that exploits different flavours of reconfigurable computing, merged together in a high parallel on-chip and off-chip interconnect utilized for both data and configuration. The aim of this work is to deliver a single monolithic engine that capitalizes on the strong points of different reconfigurable fabrics, while providing a friendly programming interface. The user is ultimately able to manage a broad spectrum of different applications, exploiting the most efficient means of computation through utilization of each kernel, while retaining a software-oriented development environment as much as possible.