Pathfinding: A design methodology for fast exploration and optimization of 3D-stacked integrated circuits

Dragomir Milojevic1,  Riko Radojcic2,  Roger Carpenter3,  Pol Marchal4
1ULB, 2Qualcomm, 3Javelin DA, 4IMEC


This paper introduces new design methodology and the corresponding EDA tool chain enabling fast design space exploration and high fidelity of relative goodness of results for emerging heterogeneous 3D-Stacked Integrated Circuits. The proposed framework allows designers to trade off between different system level design choices (e.g. functional partitioning), physical design options (e.g. packaging strategies) and/or technology options (e.g. different technology nodes) and understand their impact on typical design parameters such as cost, performance and power. We demonstrate the proposed framework using a simplified version of an existing, fairly complex MPSoC. The system is virtually prototyped as a traditional 2D and then 3D design. For a 3D version we place the off-chip DRAM memory on the top of the processing die, and consider different packaging options. For different implementation scenarios we quantify typical design parameters showing the benefit of the 3D integration.