Automatic Generation of Memory Interfaces

David Kammler1,  Bastian Bauwens1,  Ernst Martin Witte1,  Gerd Ascheid1,  Rainer Leupers1,  Heinrich Meyr1,  Anupam Chattopadhyay2
1ISS, RWTH Aachen University, 2CoWare India Private Ltd.


With the growing market for multi-processor system-on-chip (MPSoC) solutions, application-specific instruction-set processors (ASIPs) gain importance as they allow for a wide tradeoff between flexibility and efficiency in such a system. Their development is aided by architecture description languages (ADLs) supporting the automatic generation of architecture specific tool sets as well as synthesizable register transfer level (RTL) implementations from a single architecture model. However, these generated implementations have to be manually adapted to the interfaces of dedicated memories or memory controllers, slowing down the design space exploration regarding the memory architecture. In order to overcome this drawback, this work extends RTL code generation from ADL models with the automatic generation of memory interfaces. This is accomplished by introducing a new abstract and versatile description format for memory interfaces and their timing protocols.