International Symposium on System-on-Chip
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SOC 2009: Program

This is the preliminary programme page.

Take a look at the FINAL PROGRAMME PDF!!


SESSION TueAM1

Tuesday Oct. 6

10.00-11.00  Studio

Opening and Keynote


SESSION TueAM2

Tuesday Oct. 6

11.00-12.00  Rondo

Poster1, Industrial Presentations and Coffee


Simultaneous PVT-Tolerant Voltage-Island Formation and Core Placement for Thousand-Core Platforms
Sohaib Majzoub,  Resve Saleh,  Steve Wilton,  Rabab Ward
Department of Electrical and Computer Engineering, University of British Columbia


Fault-Tolerant Communication over Micronmesh NOC with Micron-Message Passing Protocol
Heikki Kariniemi and Jari Nurmi
Department of computer systems, Tampere university of technology


Adaptive Circuit Block Model for Power Supply Noise Analysis of Low Power System-on-Chip
Matthias Eireiner1,  Paul Wallner2,  Andreas Schoene2,  Stephan Henzler2,  Ulrich Fiedler2,  Doris Schmitt-Landsiedel1
1Technical University Munich, 2Infineon Technologies AG, Munich


Parameterizing Simulated Annealing for Distributing Kahn Process Networks on Multiprocessor SoCs
Heikki Orsila,  Erno Salminen,  Timo Hämäläinen
Tampere University of Technology


Energy and Bandwidth Aware Mapping of IPs onto Regular NoC Architectures Using Multi-Objective Genetic Algorithms
KSHITIJ BHARDWAJ1 and RABINDRA JENA2
1Institute of Engg. & Tech, DAVV, 2Institute of Management & Tech.


Physical realization oriented area-power-delay tradeoff exploration
Volker Gierenz1,  Christian Panis1,  Jari Nurmi2
1Catena Radio Design bv, 2Tampere University of Technology


Testing and Diagnosis of Faults in Template-Based Asynchronous Circuits
Behnam Ghavami1,  Hamid_Reza Zarandi1,  Arezoo Salarpour2,  Hossein Pedram1
1Amirkabir University of Technology, 2University of Science and Technology


Dynamic Workload Peak Detection For Slack Management
Aleksandar Milutinovic1,  Kees Goossens2,  Gerard J.M. Smit1
1University of Twente 2NXP


Building Asynchronous Routers with Independent Sub-Channels
Wei Song and Doug Edwards
University of Manchester


SESSION TuePM1

Tuesday Oct. 6

13.15-14.00  Studio

Invited


SESSION TuePM2a

Tuesday Oct. 6

14.00-15.00  Studio

Analysis and Estimation Methods


Soft NMR: Exploiting Statistics for Energy-Efficiency
Eric Kim,  Rami Abdallah,  Naresh Shanbhag
University of Illinois at Urbana Champaign


Performance Analysis of LTE Protocol Processing on an ARM based Mobile Platform
David Szczesny1,  Anas Showk1,  Sebastian Hessel1,  Uwe Hildebrand2,  Valerio Frascolla2,  Attila Bilgic1
1Institute for Integrated Systems, Ruhr-Universität Bochum, D-44780 Bochum, Germany, 2Comneon GmbH, D-90449 NĂźrnberg, Germany


Performance Modeling of Parallel Applications on MPSoCs
Marco Lattuada,  Christian Pilato,  Antonino Tumeo,  Fabrizio Ferrandi
Politecnico di Milano


SESSION TuePM2b

Tuesday Oct. 6

14.00-15.00  Rondo

Network-on-Chip and Inter-Chip Communications


Impact of Device Variability in the Communication Structures for Future Synchronous SoC Designs
Faiz ul Hassan,  Binjie Cheng,  Wim Vanderbauwhede,  Fernando Rodriguez
University of Glasgow, UK


Flexible DOR Routing for Virtualization of Multicore Chips
Frank Olaf Sem-Jacobsen1,  Tor Skeie1,  Samuel Rodrigo2,  José Flich2,  Davide Bertozzi3,  Simone Medardoni3
1Networks and Distributed Systems, Simula Research Laboratory, Lysaker, Norway, 2Parallel Architectures Group, Technical University of Valencia, Valencia, Spain, 3ENDIF, Department of Engineering, University of Ferrara, Ferrara, Italy


Automatic Generation of Memory Interfaces
David Kammler1,  Bastian Bauwens1,  Ernst Martin Witte1,  Gerd Ascheid1,  Rainer Leupers1,  Heinrich Meyr1,  Anupam Chattopadhyay2
1ISS, RWTH Aachen University, 2CoWare India Private Ltd.


SESSION TuePM3

Tuesday Oct. 6

15.00-16.00  Rondo

Poster2, Industrial Presentations and Coffee


Two Phase Clocked Adiabatic Static CMOS Logic
Nazrul Anuar Nayan1,  Yasuhiro Takahashi2,  Toshikazu Sekine2
1Graduate School of Engineering, Gifu University, 2Gifu University


Evaluation of Static and Dynamic Task Mapping Algorithms in NoC-Based MPSoCs
Ewerson Carvalho,  César Marcon,  Ney Calazans,  Fernando Moraes
PUCRS


Minimizing area costs in GPS applications on a programmable DSP by code compression
Piia Saastamoinen1,  Jari Nurmi1,  Ilkka Saastamoinen2,  Mikko Laiho2
1Tampere University of Technology, Department of Computer Systems, 2Atheros Communications, Tampere, Finland


Scheduling Framework for Real-time Dependable NoC-Based Systems
Mihkel Tagel,  Peeter Ellervee,  Gert Jervan
Tallinn University of Technology


Yield-oriented Evaluation Methodology of Networks-on-Chip Routing Implementations
Samuel Rodrigo1,  Carles Hernández1,  José Flich1,  Federico Silla1,  José Duato1,  Simone Merdardoni2,  Davide Bertozzi2,  Andres Mejia3,  Donglai Dai3
1UPV, 2UNIFE, 3INTEL


A Multi-Core Signal Processor for Heterogeneous Reconfigurable Computing
Davide Rossi1,  Fabio Campi2,  Antonio Deledda1,  Claudio Mucci3,  Stefano Pucillo3,  Sean Whitty4,  Rolf Ernst4,  Stephane Chevobbe5,  Stephane Guyetant5,  Matthias Kühnle6,  Michael Hübner6,  Jürgen Becker6,  Wolfram Putzke-Roeming7
1ARCES,University Of Bologna, Italy, 2ST Microelectronics, Agrate Brianza, Italy, 3STMicroelectronics, Agrate Brianza, Italy, 4Technische Universität Braunschweig, Germany, 5CEA, Paris, France, 6ITIV, University Of Karlsruhe, Germany, 7Thomson, Germany


RTL-to-Layout Implementation of an Embedded Coarse Grained Architecture for Dynamically Reconfigurable Computing in Systems-on-Chip
Fabio Campi1,  Ralf König2,  Michael Dreschmann2,  Moritz Neukirchner3,  Damien Picard4,  Michael Jüttner5,  Eberhard Schüler6,  Antonio Deledda7,  Davide Rossi7,  Alberto Pasini1,  Michael Hübner2,  Jürgen Becker2,  Roberto Guerrieri7
1STMicroelectronics, 2ITIV, University of Karlsruhe, 3Technical University of BraunSchweig, 4Université de Bretagne Occidentale, 5Technical University of Chemnitz, Germany, 6PACT XPP Technologies, 7ARCES, University of Bologna


Analysis of Memory Access Optimization for Motion Compensation Frames in MPEG-4.
Haitham Habli1,  Johan Ersfolk2,  Johan Lilius1
1Åbo Akademi university, 2TUCS and Åbo Akademi university


Pathfinding: A design methodology for fast exploration and optimization of 3D-stacked integrated circuits
Dragomir Milojevic1,  Riko Radojcic2,  Roger Carpenter3,  Pol Marchal4
1ULB, 2Qualcomm, 3Javelin DA, 4IMEC


SESSION TuePM4

Tuesday Oct. 6

16.00-16.45  Studio

Invited


SESSION TuePM5

Tuesday Oct. 6

16.45-18.00  Studio

Panel Discussion


SESSION WedAM1

Wednesday Oct. 7

9.15-10.00  Pieni Sali

Keynote: Henry Tirri


SESSION WedAM2

Wednesday Oct. 7

10.00-11.00  Rondo

Industrial Presentations and Coffee


SESSION WedAM3

Wednesday Oct. 7

11.00-12.20  Studio

Advanced Platform Architectures


Multi-compartment: A new architecture for secure co-hosting on SoC
Joël Porquet1,  Christian Schwarz1,  Alain Greiner2
1STMicroelectronics, 2UPMC/LIP6


Performance Analysis of Multi-Channel Memories in Mobile Devices
Jari Nikara,  Eero Aho,  Petri Tuominen,  Kimmo Kuusilinna
Nokia Research Center


System Architecture for 3GPP LTE Modem using a Programmable Baseband Processor
Di Wu,  Johan Eilert,  Dake Liu,  Anders Nilsson,  Eric Tell,  Erik Alfredsson
Linkoping University


On the Performance of 3GPP LTE Baseband Using SB3500
Zhenyu Tu,  Meng Yu,  Daniel Iancu,  Mayan Moudgill,  John Glossner
Sandbridge Technologies Inc.


SESSION WedPM1

Wednesday Oct. 7

13.20-14.40  Studio

Application-Specific Processors and Architectures


Instruction Merging to Increase Parallelism in VLIW Architectures
Guillermo Payá-Vayá,  Javier Martín-Langerwerf,  Florian Giesemann,  Holger Blume,  Peter Pirsch
Institute of Microelectronic Systems, Leibniz Universität Hannover


Efficient Software Cache for H.264 Motion Compensation
Arnaldo Azevedo and Ben Juurlink
Delft University of Technology


A DSP architecture optimized for wireless baseband
Chris Rowen,  Peter Nuth,  Stuart Fiske,  Marcus Binning,  Sam Khouri
Tensilica, inc.


Mapping of the FFT on a Reconfigurable Architecture targeted to SDR Applications
Fabio Garzia1,  Roberto Airoldi1,  Carmelo Giliberto2,  Claudio Brunelli2,  Jari Nurmi1
1TUT, 2NOKIA


SESSION WedPM2

Wednesday Oct. 7

14.40-15.40  Rondo

Industrial Presentations and Coffee


SESSION WedPM3

Wednesday Oct. 7

15.40-16.40  Studio

System-Level Design Methodology


A Checkpoint/Restore Framework for SystemC-Based Virtual Platforms
Stefan Kraemer1,  Rainer Leupers1,  Dietmar Petras2,  Thomas Philipp2
1RWTH-Aachen University, 2CoWare


Automated Instrumentation of FPGA-based Systems for System-level Transaction Monitoring
Paul McKechnie1,  Michaela Blott2,  Wim Vanderbauwhede3
1Institute for System Level Integration, 2Xilinx, 3University of Glasgow


Characterising Embedded Applications using a UML Profile
Sanna Määttä1,  Leandro Soares Indrusiak2,  Luciano Ost3,  Leandro Möller4,  Manfred Glesner4,  Fernando Gehm Moraes3,  Jari Nurmi1
1Tampere University of Technology, 2University of York, 3Catholic University of Rio Grande do Sul, 4Technische Universität Darmstadt


SESSION WedPM4

Wednesday Oct. 7

17.00-17.45  Pieni Sali

Keynote