EMBRACE-SysC for Analysis of NoC-based Spiking Neural Network Architectures

Sandeep Pande1,  Fearghal Morgan1,  Seamus Cawley1,  Brian McGinley1,  Snaider Carrillo2,  Liam McDaid2,  Jim Harkin2

1National University of Ireland, Galway, 2University of Ulster


This paper presents EMBRACE-SysC, a simulation-based design exploration framework for the EMBRACE mixed signal Network on Chip (NoC)-based hardware Spiking Neural Network (SNN) architecture. EMBRACE-SysC incorporates Genetic Algorithm-based training of SNN applications. Results illustrate the application of EMBRACE-SysC for performance analysis of a NoC-based SNN architecture. The development of EMBRACE-SysC introduces a powerful design exploration framework for EMBRACE architecture development.