Hamming Distance Based 2-D Reordering With Power Efficient Don’t Care Bit Filling: Optimizing the Test Data Compression Method

Usha Mehta1,  Kankar Dasgupta2,  Niranjan Devashrayee1

1Nirma University, Ahmedabad, India, 2SAC, ISRO, Ahmedabad, India


This paper presents a method to compress partially specified test data for a given SoC in Automatic Test Equipment (ATE). A method “Hamming Distance Based 2-Dimensional Reordering with Power Efficient Don’t Care Bit Filling” is presented for compression of test data in which two dimensional i.e. row and columnwise test vector reordering and power optimized don’t care bit filling method is applied. The advantage of the approach is a good compression with very low test power achieved without adding area overhead. The advantages are shown by experimental results with ISCAS benchmark circuits.