Optimized Communication Architecture of MPSoCs with a Hardware Scheduler: A System View

Diandian Zhang1,  Han Zhang1,  Jeronimo Castrillon1,  Torsten Kempf1,  Gerd Ascheid1,  Rainer Leupers1,  Bart Vanthournout2

1Institute for Integrated Signal Processing Systems (ISS), RWTH Aachen University, Germany, 2CoWare NV (Synopsys), Leuven, Belgium


With increasing complexity of MPSoCs, efficient runtime management of system resources becomes of vital importance for improving the system performance and energy efficiency. OSIP - an operating system application-specific instruction-set processor - provides a promising solution to this. It delivers high computational performance to deal with dynamic task scheduling and mapping, while still being programmable. However, the distributed computation among the different processing elements introduces complexity to the communication architecture, which tends to become the bottleneck of such systems. In this work, we show a detailed analysis and optimization for the communication architecture of OSIP-based MPSoCs. In particular, the joint effects of OSIP and the communication architecture are investigated from the system point of view.