State Chart Refinement Validation from Approximately Timed to Cycle Callable Models

Rainer Findenig1 and Wolfgang Ecker2

1Upper Austrian University of Applied Sciences, Hagenberg, Austria, 2Infineon Technologies AG, Munich, Germany

Abstract

Most of today's designs use a top-down design flow in which hardware is first implemented at transaction level and, as soon as it's functionality is verified, refined to a register transfer model which is conceptually a cycle true and cycle callable model. Traditionally, both the refinement and its validation are done by hand. We propose a design pattern for both the transaction-level and the cycle callable model that eases both steps: the refinement process is made more intuitive and verifying the cycle callable model is greatly simplified by automatically synchronizing the transaction-level model with the refined model.