A Digit-Set-Interleaved Radix-8 Division/Square Root Kernel for Double-Precision Floating-Point

Ingo Rust and Tobias G. Noll

Institute of Electrical Engineering and Computer Systems, RWTH Aachen University, Aachen, Germany

Abstract

A recently proposed modified SRT division algorithm with reduced comparator count and optimized partial remainder generation is extended to the square root operation. A combined radix-8 division and square root kernel for double-precision floating point based on the proposed algorithm was synthesized using a 40-nm general-purpose cell library. The implementation comprises a critical path of 20.8 fanout-4 inverter delays which is comparable to a high-speed SRT implementation which supports radix-4 only. Furthermore, the proposed algorithm reduces the total area compared to equivalent SRT-based implementations.