Process Variation and Layout Mismatch Tolerant Design of Source Synchronous Links for GALS Networks-on-Chip

Alessandro Strano1,  Carles Hern├ández2,  Federico Silla2,  Davide Bertozzi1

1University of Ferrara, 2Universidad de Valencia


Networks-on-chip are gaining momentum as reference interconnect fabric for large scale multi-core systems. There is today little doubt on the fact that clock tree design for such network-based systems will be feasible on nanoscale silicon technologies (45nm and beyond) only under relaxed synchronization assumptions. For this reason, various kinds of GALS NoC architectures are being currently proposed. In this context, synchronization interfaces in the network are becoming vulnerable points that need to be safeguarded against link delay variations and signal misalignments. This paper addresses the challenge of designing a process variation and layout mismatch tolerant link for GALS NoCs by implementing a self-calibration mechanism. A variation detector senses the variability-induced misalignment between data lines with themselves and with the transmitter clock routed with data in source synchronous links. Then, a suitable delayed replica of the transmitter clock is selected for safe sampling of misaligned data. The paper proves correct operation of the GALS link augmented with the variation detector and compares its reliability with that of a detector-less link, beyond proving robustness with respect to the delay variability affecting the detector itself.