Reducing Instruction Memory Energy Consumption by Use of the Instruction Buffer and After Scheduling Analysis

Vladimír Guzma,  Teemu Pitkänen,  Jarmo Takala

Tampere Univ. Tech.

Abstract

Use of Instruction Buffers (also named Repeat Buffers), and caches is common way to avoid memory speed bottleneck in presence of memory hierarchies. Once the instruction resides in a cache or a buffer, repeated execution of the same instruction does not require separate memory access and possible cache miss.

Use of the instruction buffer offers also an advantage when low energy consumption is an issue. Reading instruction from buffer requires order of magnitude less energy then fetch from instruction memory. Keeping memories in the deselect mode takes roughly half of the power compared to reading. In addition, storing the instructions in the buffer decoded saves energy in the processor control efficiency as well.

In this work, we analyze effects of adding instruction buffer to existing ASIP architecture. We analyze already generated code of an application to find parts of code that are executed often and augment instructions with instruction buffer control information. We show, that for many of embedded applications, storing kernels of execution in the instruction buffer saves between 60 to 87% of instruction memory accesses and possibly same amount of instruction decoding, even if only the most trivial loop structures are found. This savings can translate to up to 47% saving of memory energy.