International Symposium on System-on-Chip
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The most advanced programme is available in pdf here.


SOC 2011: Advanced Program

Tuesday November 1
   Opening
9:00 WELCOME TO SOC 2011   
   - Studio
  
Chair: Jari Nurmi
Tuesday November 1
   Keynote
9:15 3D Integration of NoC-based Systems, Axel Jantsch, KTH, Sweden   
   - Studio
Tuesday November 1
   Coffee
10:00   
   - Rondo
Tuesday November 1
   System-level design flow and methodology
10:30   
   - Studio
   Analyzing Layer-2 Performance and Scalability in System-Level Performance Simulation
subayal khan1,  jukka saastamoinen1,  Mikko Majanen Majanen1,  Jari Nurmi2
1VTT Technical Receaech Centre of Finland, 2Tampere University of Technology. Department of Computer Systems
File
   Moonrake Chip - GALS Demonstrator in 40 nm CMOS Technology
Milos Krstic1,  Xin Fan1,  Eckhard Grass1,  Luca Benini2,  M. R. Kakoee2,  Christoph Heer3,  Birgit Sanders3,  Alessandro Strano4,  Davide Bertozzi4
1IHP, 2University of Bologna, 3Intel Mobile Communications, 4University of Ferrara
File
   Analyzing Synchronous Dataflow Scenarios for Dynamic Software-defined Radio Applications
Firew Siyoum1,  Marc Geilen1,  Orlando Moreira2,  Rick Nas2,  Henk Corporaal1
1Eindhoven University of Technology, 2ST-Ericsson Eindhoven
File
Tuesday November 1
   Processor architectures
11:30   
   - Studio
   A Hybrid Model of Speculative Execution and Scout Threading for Auto-Memoization Processor
Tomoki IKEGAYA1,  Ryosuke ODA1,  Tatsuhiro YAMADA1,  Tomoaki TSUMURA1,  Hiroshi MATSUO1,  Yasuhiko NAKASHIMA2
1Nagoya Inst. of Tech., 2Nara Inst. of Sci. and Tech.
File
   Customizable Datapath Integrated Lock Unit
Pekka Jääskeläinen,  Erno Salminen,  Otto Esko,  Jarmo Takala
Tampere Univ. of Tech.
File
   Exploring Instruction caching strategies for tightly-coupled shared-memory clusters
Daniele Bortolotti,  Francesco Paterna,  Christian Pinto,  Andrea Marongiu,  Martino Ruggiero,  Luca Benini
University of Bologna - DEIS
File
Tuesday November 1
   Lunch
12:30   
   - Restaurant Fuuga
Tuesday November 1
   Invited 2
13:30 Fast and accurate system-level model of a NoC-based MPSoC supporting real-time applications, Leandro Soares Indrusiak, University of York, UK   
   - Studio
Tuesday November 1
   SoC design and analysis methods
14:15   
   - Studio
   Static Analysis Method for Deadlock Detection in SystemC Designs
Mikhail Moiseev1,  Alexey Zakharov1,  Ilya Klotchkov2,  Sergey Salishev2
1SPbSPU, 2Intel Labs
File
   SAMOSA: Scratchpad Aware Mapping Of Streaming Applications
Zubair Wadood Bhatti1,  Davy Preuveneers1,  Narasinga Rao Miniskar2,  Roel Wuyts2,  Yolande Berbers1
1K.U.Leuven, 2IMEC
File
   Hybrid System Level Power Consumption Estimation for FPGA-Based MPSoC
Santhosh Kumar Rethinagir1,  Rabie ben Atitallah2,  Jean-Luc Dekeyser3
1Affiliation, 2Univ.Valenciennes, 3Univ. Lille
File
Tuesday November 1
   Posters and coffee
15:15   
   - Rondo
   OpenCL Implementation of Cholesky Matrix Decomposition
Claudio Brunelli,  Eero Aho,  Heikki Berg
Nokia
File
   Low-power Arithmetic Unit for DSP Applications
Mehdi Modaressi1,  Hossein Nikonia2,  Amir-Hossein Jahangir1
1Sharif University of Technology, 2Tehran University
File
   Co-designs of Parallel Rijndael
Issam Damaj
American University of Kuwait
File
   A Set of Traffic Models for Network-on-Chip Benchmarking
Esko Pekkarinen,  Lasse Lehtonen,  Erno Salminen,  Timo D. Hämäläinen
TUT
File
   Effects of Loop Unrolling and Use of Instruction Buffer on Processor Energy Consumption
Vladimír Guzma,  Teemu Pitkänen,  Jarmo Takala
Tampere University of Technology
File
   Product data management using IP-XACT
Erno Salminen,  Timo D. Hämäläinen,  Marko Hännikäinen
TUT
File
   Increasing Energy Efficiency of Automotive E/E-Architectures with Intelligent Communication Controllers for FlexRay
Christoph Schmutzler1,  Abdallah Lakhtel1,  Martin Simons1,  Jürgen Becker2
1Daimler AG, 2Karlsruhe Institute of Technology, ITIV
File
   AN AUTOMATIC EXPERIMENTAL SET-UP FOR ROBUSTNESS ANALYSIS OF DESIGNS IMPLEMENTED ON SRAM FPGAS
Uli Kretzschmar,  Armando Astarloa,  Jesús Lázaro,  Jaime Jiménez,  Aitzol Zuloaga
Universidad del Pais Vasco UPV/EHU
File
   A Coarse-Grained Reconfigurable Protocol Processor
Mohammad Badawi and Ahmed Hemani
Royal Institute of Technology, Stockholm, Sweden
File
   moviTest: A Test Environment Dedicated to Multi-Core Embedded Architectures
Teodor Tite1,  Adelina Vig1,  Nicolae Olteanu2,  Cristian Cuna2
1University “Politehnica” of Timisoara, Department of Computer and Software Engineering, Timisoara, Romania, 2Movidius SRL, Tools Department, Timisoara, Romania
File
Tuesday November 1
   Invited 3
16:00 Jan Madsen DTU, Denmark   
   - Studio
Tuesday November 1
   Panel Discussion
16:45   
   - Studio
Tuesday November 1
   Reception
18:00   
   - Rondo
Wednesday November 2
   DASIP 2011 Opening
9:00 WELCOME TO DASIP 2011   
   - Studio
  
Chair: Tapani Ahonen and Jari Nurmi
Wednesday November 2
   Invited 4
9:20 Yves Leduc, University of Nice, France   
   - Studio
Wednesday November 2
   Posters and coffee
10:05   
   - Rondo
Wednesday November 2
   Network-on-chip and inter-chip communications
11:00   
   - Studio
   Mismatch Characterization of High-Speed NoC Links using Asynchronous Sub-sampling
Sebastian Höppner,  Dennis Walter,  Georg Ellguth,  Renè Schüffny
TU Dresden
File
   Impact of Proactive Temperature Management on Performance of Networks-on-Chip
Tim Wegner,  Martin Gag,  Dirk Timmermann
University of Rostock
File
   Bringing Network-on-Chip Links to 45nm
Marco Ferraresi,  Giuseppina Gobbo,  Daniele Ludovici,  Davide Bertozzi
University of Ferrara
File
   Synchronizing Distributed State Machines In A Coarse Grain Reconfigurable Architecture
Omer Malik and Ahmed Hemani
Royal Institute of Technology - KTHKTH
File
Wednesday November 2
   Lunch
12:20   
   - Restaurant Fuuga
Wednesday November 2
   Invited 5
14:00 Design challenges in SoCs for mobile devices, Toshihiro Hattori, Renesas Mobile Corporation, Japan   
   - Studio
Wednesday November 2
   Software tools
14:45   
   - Studio
   Automatic Calibration of Streaming Applications for Software Mapping Exploration
Weihua Sheng,  Stefan Schürmans,  Maximilian Odendahl,  Rainer Leupers,  Gerd Ascheid
RWTH Aachen University
File
   Building a RTOS for MPSoC Dataflow Programming
Yaset Oliva1,  Maxime Pelcat1,  Jean-Francois Nezan1,  Jean-Christophe Prévotet1,  Aridhi Slaheddine2
1IETR/INSA Rennes, 2Texas Instruments
File
Wednesday November 2
   DASIP posters and coffee
15:25   
   - Rondo
Wednesday November 2
   Invited 6
16:00 Heterogeneous Concurrent Modeling and Design in Java, Patricia Derler, UC Berkeley, USA   
   - Studio
Wednesday November 2
   Closing
16:45   
   - Studio
Wednesday November 2
   Banquet
19:30