International Symposium on System-on-Chip
SoC | 1999 | 2000 | 2001 | 2002 | 2003 | 2004 | 2005 | 2006 | 2007 | 2008 | 2009 | 2010 | 2011 | 2012 | 2013 | 2014 | 2015

General

Conference

Lodging / Travel


Valid XHTML 1.1

Valid CSS!

Invited talk abstracts and biographies

Heterogeneous Concurrent Modeling and Design in Java
Dr. Patricia Derler, UC Berkeley, USA

This presentation describes an open-source framework in Java for modeling and simulating heterogeneous systems, called Ptolemy. Models are defined using the actor-oriented design principle. Actors transform values on inputs, update their state and/or produce values on outputs. The implementation of an actor can be manifold; examples are imperative programs, finite state machines, or physical processes. In Ptolemy, a special actor, the director, coordinates the execution of all other actors in a model. This coordination includes actor communication as well as concurrency mechanisms. The definition of an actor together with the coordination of actor executions describe a model of computation (MoC). Some MoCs that are contained in Ptolemy are discrete event, continuous time, dataflow, synchronous reactive and process network. Different MoCs can be composed hierarchically, however, some restrictions apply. For instance, a timed MoC cannot be embedded in an un-timed MoC. This talk will describe some MoCs and the concurrency mechanisms that govern interactions between actors.

Bio:
Patricia Derler
Patricia Derler is a postdoctoral researcher at the UC Berkeley. She received her Ph.D. in Computer Science from the University of Salzburg, Austria and she did her undergraduate studies at the University of Hagenberg, Austria. Her research interests are in design and simulation of cyber-physical systems, deterministic models of computation and the use of predictability in software, hardware and the environment towards efficient simulations and executions.


Design challenges in SoCs for mobile devices
Toshihiro Hattori, Renesas Mobile Corporation, Japan

Renesas Mobile Corporation (RMC), established on the first of December 2010, comes to the global chipset market with advanced and innovative products and services for mobile phones, car infotainment solutions, consumer electronics and industrial applications. The modem group in RMC comes with a strong pedigree from Nokia. The group has developed all Nokia?s in-house modems and formed an essential part of the chipset development for Nokia products since the time of NMT and the first generation of GSM. The world-class and leading wireless connectivity expertise is visible today as widely accepted modem technology and IP in billions of handsets. Renesas Mobile continues on this path by combining the modem asset with Renesas?s unique experience in the field of applications processors, microprocessors and controllers to form a base for highly integrated single- or multichip mobile platforms. This presentation introduces design challenges for Baseband LSI, Application LSI, and Onechip LSI for mobile world.

Bio:
Toshihiro Hattori
Toshihiro Hattori received the B.S. and M.S. degrees in electrical engineering from Kyoto University, Japan, in 1983 and 1985, respectively. He received the Ph.D in informatics from Kyoto University, Japan, in 2006. He joined the Central Research Laboratory, Hitachi, Ltd., Tokyo, Japan, in 1985. He engaged in logic/layout tool development. From 1992 to 1993 he was a Visiting Researcher at the University of California Berkeley, with a particular interest in CAD. He joined the Semiconductor Development Center in the Semiconductor Integrated Circuits Division in Hitachi Ltd. in 1995. He moved to Renesas Technology Corp. in 2003. He was belonging to SuperH (Japan), Ltd. from 2001 to 2004 to conduct SH processor licensing and development. He moved to Renesas Electronics Corp. in 2010. He is currently working with Renesas Mobile Corp. as VP of SoC design. He is a member of IEEE(SSCS), ACM, IEICE, and IPSJ.


Fast and accurate system-level model of a NoC-based MPSoC supporting real-time applications
Leandro Soares Indrusiak, University of York, UK

Time-predictable architectures can be useful for a variety of reasons. Firstly, their time-predictability allow us to forecast its worst-case performance, making them suitable for real-time applications. Secondly, such architectures are more amenable to abstraction: their behaviour does not exhibit excessive variability and can therefore be captured by a simpler model with small loss of accuracy. This talk will present one of such architectures - a network-on-chip (NoC) with priority preemptive virtual channel arbitration - and will show how its predictability can be used to enable the creation of a transaction-level model (TLM) that can significantly reduce its validation time. Experimental results will be discussed, showing that the proposed TLM model can produce accurate communication latency figures more than two orders of magnitude faster than a cycle-accurate model.

Bio:
Leandro Soares Indrusiak
Leandro Soares Indrusiak received a BEng in Electrical Engineering (UFSM, 1995) and a MSc in Computer Science (UFRGS, 1998) in Brazil, where he has also worked as assistant professor (PUCRS, 1998-2000) and started his doctoral studies. He moved to Germany and finished a binational doctoral degree in Computer Science (jointly awarded by UFRGS and TU Darmstadt, 2003). He worked at TU Darmstadt as a research fellow until 2008, leading a research group on System-on-Chip design. He then moved to the United Kingdom as a permanent faculty member of University of York's Computer Science department. His current research interests include specification, design and analysis of multiprocessor, real-time and distributed embedded systems.


The Promises and Limitations of 3-D Integration
Prof. Axel Jantsch, KTH, Sweden

The intrinsic computational efficiency (ICE) of silicon defines the upper limit of the amount of computation within a given technology and power envelope. The effective computational efficiency (ECE) and the effective computational density (ECD) of silicon, by taking computation, memory and communication into account, offer a more realistic upper bound for computation of a given technology. Among other factors, they consider how distributed the memory is, how much area is occupied by computation, memory and interconnect, and the geometric properties of 3-D stacked technology with through silicon vias (TSV) as vertical links. We use ECE and ECD to study the limits of performance under different memory distribution constraints of various 2-D and 3-D topologies, in current and future technology nodes. Among other results, our model shows that in a 35 nm technology a 16 stack 3-D system can, as a theoretical upper limit, obtain 3.4 times the performance of a 2-D system (8.8 Tera OPS vs 2.6 TOPS) at 70% reduced frequency (2.1 GHz vs 3.7 GHz) on 1/8 the total area (50 mm2 vs 400 mm2 ).

Bio:
Axel Jantsch
Axel Jantsch (M?97) received a Dipl.Ing. (1988) and a Dr. Tech. (1992) degree from the Technical University Vienna. Between 1993 and 1995 he received the Alfred Schrödinger scholarship from the Austrian Science Foundation as a guest researcher at the Royal Institute of Technology (KTH). From 1995 through 1997 he was with Siemens Austria in Vienna as a system validation engineer. Since 1997 he is Associate Professor at KTH, since 2000 he is Docent, since December 2002 he is full professor in Electronic System Design. A. Jantsch has published over 200 papers in international conferences and journals and one book in the areas of VLSI design and synthesis, system level specification, modeling and validation, HW/SW codesign and cosynthesis, reconfigurable computing and networks on chip. He has served on a large number of technical program committees of international conferences such as FDL, DATE, CODES+ISSS, SOC, and NOCS and others. He has been TPC chair of SSDL/FDL 2000, TPC cochair of CODES+ISSS 2004 and general chair of CODES+ISSS 2005 and TPC co-chair of NOCS 2009. From 2002 to 2007 he was Subject Area Editor for the Journal of System Architecture. At the Royal Institute of Technology A. Jantsch is heading a number of research projects involving a total number of 10 Ph.D. students, in two main areas: System Modeling and Networks on Chip.


Addressing Risk Management during Design Space Exploration
Prof. Jan Madsen, DTU Informatics, Technical University of Denmark

One of the challenges in modern embedded system design is to map the application onto a multi-core platform such that essential requirements are met. This process is called Design Space Exploration (DSE). In order to do DSE at an early stage in the design process, where not all parts have been implemented or even designed, a system-level model of the application executing on the multi-core platform is needed. This model should allow for an accurate modeling of the global performance of the system, including the interrelationships among the diverse processors, software processes and physical interfaces and inter-connections. This talk will focus on risk management in relation to DSE.

Bio:
Jan Madsen
Jan Madsen is a full Professor in computer based systems at the Department of Informatics and Mathematical Modeling at the Technical University of Denmark, where he is heading the System-on-Chip group. His research interests include high-level synthesis, hardware/software codesign, System-on-Chip design methods, and system level modeling, integration and synthesis for embedded computer systems. Jan Madsen is Program Chair for DATE?07, Vice-Program Chair and Tutorial Chair for DATE?06, and Workshop Chair for CODES+ISSS?05. He was General Chair of CODES 2001 and Program Chair of CODES 2000. He is an editorial board member of the journal ?IEE Proceedings ? Computers and Digital Techniques? and is a member of the steering committee of the IEEE NORCHIP conference. He has served as a technical program committee member on several international (ACM/IEEE) conferences, including DAC, ISSS+CODES, SoC Symposium, ISSS, CODES, DATE, FTRTFT, ED&TC, ACSD and Euromicro DSD.


SoC, MPSoC, RSoC, ... , Design Challenges, The Industrial Point of View
Prof. Yves Leduc, TI chair at University of Nice, France

After a presentation of the new business landscape, we will review the major issues that the semiconductor companies are facing in the nanoelectronic era. System size and complexity are the first barriers. We will identify and understand these barriers and elaborate on ad hoc solutions. A second issue is associated to the ultimate technology scaling. Atoms and molecules in nanoelectronics are no more contributing in a safe average cooperation but tend to act as individuals to perturb the electrical behavior of the basic transistors. Again we will identify and understand the issues and review how the exacerbated process variabilities is influencing the work of our designers. Last but not least, the thermal dissipation in large SOCs will be discussed. It represents, de facto, the actual limits to the realization of our business dream. To conclude, we will detail how 3D-IC will or will not bring new solutions to the designs of our next future.

Bio:
Yves Leduc
Yves got his PhD in electrical engineering from the University of Louvain in 1979. With Texas instruments France for the last 30 years, he created in 1994 the mixed signal development team of TI France and was elected TI Fellow in 1998. Yves then led the advanced system technology team paving the way to the future development of the new SOCs. Yves is currently holding the TI Chair at the University of Nice and participate to several organizations to promote the creation of start-ups in microelectronics.