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Preliminary Program

SoC 2012 Tampere

The following papers have been accepted for either oral or poster presentation. An asterisk (*) marks the poster papers.


A DOUBLE DATA RATE 8T-CELL SRAM ARCHITECTURE FOR SYSTEMS-ON-CHIP *
Saleh Abdel-Hafeez, Mohammad Shatnawi and Ann Gordon-Ross

A FLEXIBLE PLATFORM ARCHITECTURE FOR GBPS WIRELESS COMMUNICATION
Jeroen Declerck, Prabhat Avasare, Miguel Glassee, Amir Amin, Erik
Umans, Martin Palkovic, Andy Dewilde and Praveen Raghavan

A HYBRID CHIP INTERCONNECTION ARCHITECTURE WITH A GLOBAL WIRELESS
NETWORK OVERLAID ON TOP OF A WIRED NETWORK-ON-CHIP *
Ling Wang, Peng Lv and Yingtao Jiang

A MULTI-BANKED SHARED-L1 CACHE ARCHITECTURE FOR TIGHTLY COUPLED
PROCESSOR CLUSTERS
Mohammad Reza Kakoee, Vladimir Petrović and Luca Benini

AN AUTOMATED FRAMEWORK FOR THE SIMULATION OF MAPPING SOLUTIONS ON
HETEROGENEOUS MPSOCS
Antonio Miele, Christian Pilato and Donatella Sciuto

APPLICATION-AWARE SPINLOCK CONTROL USING A HARDWARE SCHEDULER IN MPSOC
PLATFORMS
Diandian Zhang, Li Lu, Jeronimo Castrillon, Torsten Kempf, Gerd
Ascheid, Rainer Leupers and Bart Vanthournout

ARCHITECTURE EFFICIENCY OF APPLICATION-SPECIFIC PROCESSOR: A 170MBIT/S
0.644MM2 MULTI-STANDARD TURBO DECODER *
Rachid Al-Khayat, Amer Baghdadi and Michel Jezequel

ASYNCHRONOUS PARALLEL MPSOC SIMULATION ON THE SINGLE-CHIP CLOUD
COMPUTER
Christoph Roth, Simon Reder, Gökhan Erdogan, Oliver Sander, Gabriel M.
Almeida and Jürgen Becker

COARSE AND FINE-GRAINED MONITORING AND RECONFIGURATION FOR
ENERGY-EFFICIENT NOCS
Liang Guang, Ethiopia Nigussie, Juha Plosila, Jouni Isoaho and Hannu
Tenhunen

COMPARATIVE ANALYSIS OF DYNAMIC TASK MAPPING HEURISTICS IN
HETEROGENEOUS NOC-BASED MPSOCS *
Leandro Moller, Leandro Soares Indrusiak, Luciano Ost, Fernando Moraes
and Manfred Glesner

CRAVE: AN ADVANCED CONSTRAINED RANDOM VERIFICATION ENVIRONMENT FOR
SYSTEMC
Finn Haedicke, Hoang Le, Daniel Grosse and Rolf Drechsler

DATAFLOW-BASED RECONFIGURABLE ARCHITECTURE FOR STREAMING APPLICATIONS
Anja Niedermeier, Jan Kuper and Gerard J.M. Smit

EFFECTS OF SCALING A COARSE-GRAIN RECONFIGURABLE ARRAY ON POWER AND
ENERGY CONSUMPTION *
Waqar Hussain, Tapani Ahonen and Jari Nurmi

EFFICIENT VLSI ARCHITECTURES OF QPP INTERLEAVERS FOR LTE TURBO DECODERS
Martin Broich and Tobias G. Noll

ENHANCING CACHE COHERENT ARCHITECTURE WITH ACCESS PATTERNS FOR EMBEDDED
MANYCORE SYSTEMS
Jussara Marandola, Stephane Louise, Loic Cudennec, Jean-Thomas
Acquaviva and David Bader

HIERARCHICAL CONTROL FLOW MATCHING FOR SOURCE-LEVEL SIMULATION OF
EMBEDDED SOFTWARE *
Kun Lu, Daniel Mueller-Gritschneder and Ulf Schlichtmann

IMPROVING LOGIC-TO-MEMORY RATIO IN AN EMBEDDED MULTI-PROCESSOR SYSTEM
VIA CODE COMPRESSION *
Roberto Airoldi, Piia Saastamoinen and Jari Nurmi

INSTRUMENTATION-DRIVEN MODEL DETECTION FOR DATAFOW GRAPHS
Ilya Chukhman, William Plishker and Shuvra Bhattacharyya

POWERMEMO: A POWER PROFILING TOOL FOR MOBILE DEVICES IN AN EMULATED
WIRELESS ENVIRONMENT *
Shiao-Li Tsao

RESOURCE-SHARED CUSTOM INSTRUCTION GENERATION UNDER PERFORMANCE/AREA
CONSTRAINTS *
Di Wu, Junhwan Ahn, Imyong Lee and Kiyoung Choi

SCALABILITY ANALYSIS OF RELEASE AND SEQUENTIAL CONSISTENCY MODELS IN
NOC BASED MULTICORE SYSTEMS *
Abdul Naeem, Axel Jantsch and Zhonghai Lu

STATISTICAL TIMING CHARACTERIZATION *
Nadine Azemard, Zeqin Wu, Philippe Maurine and Gilles Ducharme

SYSTEM-LEVEL SOFTWARE PERFORMANCE SIMULATION CONSIDERING OUT-OF-ORDER
PROCESSOR EXECUTION
Roman Plyaskin, Thomas Wild and Andreas Herkersdorf

THERMAL/PERFORMANCE TRADE-OFF IN NETWORK-ON-CHIP ARCHITECTURES
Davide Zoni, Simone Corbetta and William Fornaciari

TINY AND APPLICATION-SPECIFIC PROGRAMMABLE PROCESSOR FOR BCH DECODING
Anthony Van Herrewege and Ingrid Verbauwhede

ULTRA-LOW LATENCY NOC TESTING VIA PSEUDO-RANDOM TEST PATTERN
COMPACTION.
Hervé Tatenguem, Alessandro Strano, Vineeth Govind, Jaan Raik and
Davide Bertozzi