International Symposium on System-on-Chip
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SOC 2012: Program

SOC 2012: Program

Thursday 11.10.2012
   Registration
8:30 - 10:00   
   Coffee
9:00 - 10:00   
   - Rondo
   Opening
10:00 - 10:15   
   - Studio
   Invited1
10:15 - 11:00   
   - Studio
   ROMA: Reconfigurable Operator Based Architecture for Multimedia Applications
Emmanuel Casseau
IRISA
   Advanced Platform Architectures
11:00 - 11:40   
   - Studio
   Application-Aware Spinlock Control using a Hardware Scheduler in MPSoC Platforms
Diandian Zhang1,  Li Lu1,  Jeronimo Castrillon1,  Torsten Kempf1,  Gerd Ascheid1,  Rainer Leupers1,  Bart Vanthournout2
1Institute for Communication Technologies and Embedded Systems (ICE), RWTH Aachen University, Germany, 2Synopsys Inc., Leuven, Belgium
   A Multi-banked Shared-L1 Cache Architecture for Tightly Coupled Processor Clusters
Mohammad Reza Kakoee,  Vladimir Petrović,  Luca Benini
DEIS, University of Bologna
   Lunch
11:40 - 13:00   
   Invited2
13:00 - 13:45   
   - Studio
   Rethinking FPGAs: And-Inverter Cones Challenge LUT's Supremacy
David Novo
EPFL
   System-level Design Flow and Methodology
13:50 - 14:50   
   - Studio
   An Automated Framework for the Simulation of Mapping Solutions on Heterogeneous MPSoCs
Antonio Miele,  Christian Pilato,  Donatella Sciuto
Politecnico di Milano
   Instrumentation-Driven Model Detection for Datafow Graphs
Ilya Chukhman,  William Plishker,  Shuvra Bhattacharyya
University of Maryland College Park
   Thermal/Performance Trade-off in Network-on-Chip Architectures
Davide Zoni,  Simone Corbetta,  William Fornaciari
Politecnico di Milano
   Posters and Coffee
14:50 - 15:30   
   - Rondo
   A Double Data Rate 8T-Cell SRAM Architecture for Systems-on-Chip
Saleh Abdel-Hafeez1,  Mohammad Shatnawi1,  Ann Gordon-Ross2
1Jordan University of Science and Technology, 2University of Florida
   Scalability Analysis of Release and Sequential Consistency Models in NoC based Multicore Systems
Abdul Naeem,  Axel Jantsch,  Zhonghai Lu
Royal Institute of Technology (KTH), Sweden
   Resource-shared Custom Instruction Generation under Performance/Area Constraints
Di Wu1,  Junwhan Ahn2,  Imyong Lee2,  Kiyoung Choi2
1SAP Labs Korea, 2Seoul National University
   Comparative Analysis of Dynamic Task Mapping Heuristics in Heterogeneous NoC-based MPSoCs
Leandro Moller1,  Leandro Soares Indrusiak2,  Luciano Ost3,  Fernando Moraes4,  Manfred Glesner1
1TU Darmstadt, 2University of York, 3LIRMM, 4PUCRS
   A Hybrid Chip Interconnection Architecture with a Global Wireless Network Overlaid on Top of a Wired Network-on-Chip
Ling Wang1,  Peng Lv1,  Yingtao Jiang2
1Harbin Institute of Technology, 2University of Nevada, Las Vegas
   Statistical Timing Characterization
Nadine Azemard1,  Zeqin Wu1,  Philippe Maurine2,  Gilles Ducharme3
1LIRMM, 2UM2 _ LIRMM, 3UM2 - I3M
   Hierarchical Control Flow Matching for Source-level Simulation of Embedded Software
Kun Lu,  Daniel Mueller-Gritschneder,  Ulf Schlichtmann
Technical University of Munich
   PowerMemo: A Power Profiling Tool for Mobile Devices in an Emulated Wireless Environment
Shiao-Li Tsao
National Chiao Tung University
   Architecture Efficiency of Application-Specific Processor: a 170Mbit/s 0.644mm2 Multi-standard Turbo Decoder
Rachid Al-Khayat,  Amer Baghdadi,  Michel Jezequel
Institut Mines-Telecom; Telecom Bretagne; CNRS Lab-STICC
   Improving Logic-to-Memory Ratio in an Embedded Multi-Processor System via Code Compression
Roberto Airoldi,  Piia Saastamoinen,  Jari Nurmi
Tampere University of Technology
   Effects of Scaling a Coarse-Grain Reconfigurable Array on Power and Energy Consumption
Waqar Hussain,  Tapani Ahonen,  Jari Nurmi
Department of Computer Systems, Tampere University of Technology
   Verification and Testing
15:30 - 16:30   
   - Studio
   CRAVE: An Advanced Constrained RAndom Verification Environment for SystemC
Finn Haedicke1,  Hoang Le1,  Daniel Grosse1,  Rolf Drechsler2
1University of Bremen, 2University of Bremen and DFKI
   Asynchronous Parallel MPSoC Simulation on the Single-chip Cloud Computer
Christoph Roth,  Simon Reder,  Gökhan Erdogan,  Oliver Sander,  Gabriel M. Almeida,  Harald Bucher,  Jürgen Becker
Karlsruhe Institute of Technology
   Ultra-Low Latency NoC testing via Pseudo-Random Test Pattern Compaction.
Hervé Tatenguem1,  Alessandro Strano1,  Vineeth Govind2,  Jaan Raik2,  Davide Bertozzi1
1University of Ferrara, 2Tallinn Institute of Technology
   Panel Discussion
16:30 - 17:45   
   - Studio
   Banquet
19:00 - 22:00   
Friday 12.10.2012
   Invited3
9:00 - 9:45   
   - Studio
   Xilinx 3D Architecture
Jari Keskinen
Xilinx
   Posters and Coffee
9:45 - 10:40   
   - Rondo
   Application-Specific Architectures
10:40 - 12:00   
   - Studio
   A flexible platform architecture for Gbps Wireless Communication
Jeroen Declerck,  Prabhat Avasare,  Miguel Glassee,  Amir Amin,  Erik Umans,  Andy Dewilde,  Praveen Raghavan,  Martin Palkovic
IMEC, Belgium
   Efficient VLSI Architectures of QPP Interleavers for LTE Turbo Decoders
Martin Broich and Tobias G. Noll
EECS - RWTH Aachen University
   Tiny and Application-Specific Programmable Processor for BCH Decoding
Anthony Van Herrewege and Ingrid Verbauwhede
KU Leuven
   Dataflow-Based Reconfigurable Architecture for Streaming Applications
Anja Niedermeier,  Jan Kuper,  Gerard J.M. Smit
University of Twente
   Lunch
12:00 - 13:20   
   Techniques for Manycore System on Chips
13:20 - 14:20   
   - Studio
   Enhancing Cache Coherent Architecture with access patterns for embedded manycore systems
Jussara Marandola1,  Stephane Louise2,  Loic Cudennec2,  Jean-Thomas Acquaviva2,  David Bader1
1Georgia Tech computing center, 2CEA, LIST
   System-level Software Performance Simulation Considering Out-of-order Processor Execution
Roman Plyaskin,  Thomas Wild,  Andreas Herkersdorf
TU Munich, Germany
   Coarse and Fine-Grained Monitoring and Reconfiguration for Energy-Efficient NoCs
Liang Guang1,  Ethiopia Nigussie1,  Juha Plosila1,  Jouni Isoaho1,  Hannu Tenhunen2
1University of Turku, Finland, 2Royal Institute of Technology, Sweden
   Posters and Coffee
14:20 - 15:00   
   - Rondo
   Invited4
15:00 - 15:45   
   - Studio
   Partially Reconfigurable ASIPs
Gerd Ascheid
RWTH Aachen University
   Closing
15:45 - 16:00   
   - Studio
   Social Event
17:30 - 22:00