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Invited talk abstracts and biographies

ROMA: Reconfigurable Operator Based Architecture for Multimedia Applications
Prof. Emmanuel Casseau, IRISA, France

In multimedia applications, video and image processing is one of the challenges embedded systems have to face. Such applications are typically computationally intensive with control statements and designers have to cope with power and performance stringent requirements. The ROMA project proposes to develop both a design methodology and a reconfigurable processor able to adapt its computing structure to video and image processing applications. The reconfigurable processor is in charge of implementing parts of the code corresponding to loops and frequently executed computation code fragments that can be accelerated and/or which are good candidates to save power. It is built around a pipeline of coarse grain reconfigurable operators exhibiting interesting performance/power trade-off. The operators are designed such that their granularity matches the domain-specific computation patterns. Flexibility is obtained through these operators which can be configured for the function they implement and the width of the data. We have also developed a design flow to configure the processor. From the application source code, the software framework identifies the different computation patterns as well as their successive arrangements and completes transformations for the processor mapping.

Emmanuel Casseau
Emmanuel Casseau received the M.S. degree in Electrical Engineering in 1990 and the Ph.D degree in Electrical and Computer Engineering from the University of West Brittany, France, in 1994. From 1994 to 1996 he was a research engineer at ENST Bretagne, a graduate engineering school in France, where he developed high-speed Viterbi decoder architectures for turbo-code VLSI implementations. From 1996 to 2006 he was an Associate Professor in the Electronic Department at the University of South Brittany, France, where he led the IP project of the LESTER Laboratory. He his currently a Professor in IRISA/INRIA (French National Institute for Research in Computer Science and Control), University of Rennes1, France. His research interests include system design, high-level synthesis, SoCs design methodologies and reconfigurable architectures for multimedia applications.

Rethinking FPGAs: And-Inverter Cones Challenge LUT's Supremacy
Dr. David Novo, EPFL, Switzerland

Look-Up Tables (LUTs) are universally used in FPGAs as the fundamental unchallenged unit of functional reconfiguration. A k-input LUT can implement any k-input logic function, and thus, mapping a whole circuit onto an FPGA is a relatively straightforward covering problem. Complex circuits, however, require many LUTs connected by a flexible interconnect network, which ends up dominating circuit delay. Increasing the number of LUT inputs to cover larger parts of a circuit could reduce the communication overhead. However, it also entails an exponential increase in LUT area and power. For this reason, LUTs with more than 4-6 inputs have rarely been used in practical FPGAs. Still, the flexibility of current FPGAs comes at a huge price: the ratio of reconfigurable implementations and their ASIC counterparts is on the order of 3-5x in critical path delay, 14-7x in dynamic power consumption and 35-18x in silicon area.
In the quest for new elements to bridge the efficiency gap, we argue in this talk that other elementary logic blocks can provide a better compromise between hardware complexity and flexibility. Inspired by recent trends in synthesis and verification, we explore blocks based on And-Inverter Graphs (AIGs): their hardware complexity grows only linearly in the number of inputs, they sport the potential for multiple independent outputs, and the delay grows only logarithmically with the number of inputs. Of course, these new blocks are extremely less flexible than LUTs; yet, we show (i) that effective mapping algorithms are possible, (ii) that, due to their simplicity, poor utilization is less of an issue than with LUTs, and (iii) that a combination with a few LUTs can still be beneficial in extreme unfortunate cases. Our first results indicate that this new logic block alone, or combined with some LUTs in hybrid FPGAs, can reduce delay by 27 and 32% on average, respectively. At the same time, the area is reduced by some 16% on average. Yet, in this initial attempt we have explored only a few design points, and we think that these results could still be improved by a more systematic exploration.

David Novo
David Novo is Post-doctoral researcher at the EPFL School of Computer and Communication Sciences, where he joined the Processor Architecture Laboratory (LAP) in November 2010. Previously, he conducted his doctoral research at the Wireless Group in the Interuniversity Microelectronics Centre (IMEC), receiving the Ph.D in Engineering from the Katholieke Universiteit Leuven (KUL) in 2010.
David was recipient of the Best Paper Award at the 20th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) in 2012 and nominated at the IEEE Workshop on Signal Processing Systems (SiPS) in 2005. In 2012, he has been awarded with the EU Marie Curie Intra-European Fellowship for Career Development. In 2011, he has been Guest Editor of a Special Issue on Quantization of VLSI Digital Signal Processing Systems, which appeared in February 2012 on the EURASIP Journal on Advances in Signal Processing. He is also author of more than 30 international papers distributed in the areas of signal processing, computer-aided design and computer architectures. David is currently working on hardware and software techniques for increasing computation efficiency in next-generation computers.

Xilinx 3D Architecture
Jari Keskinen, Xilinx, Finland

As system architects seek to achieve ever higher levels of integration and performance whilst minimising costs and remaining within strict power budgets, they find limitations with traditional solutions such as PCBs or ASICs. Whilst the 3D IC is not yet a fully developed technology, there are products in production today which can help to solve these issues in some applications. This session will review a technology called Stacked Silicon Interconnect (SSIT), an enabler for 3D ICs, in which a number of manufacturing techniques have been brought together to create both homogeneous and heterogeneous All Programmable 3D ICs. The session will also explore how these 3D ICs address the challenges faced by system architects today.

Jari Keskinen
Jari Keskinen received his M.Sc. degree in Computer Engineering and Applied Electronics in 1993 from Tampere University of Technology. Today he is a Staff Field Application Engineer at Xilinx and works closely with systems architects and hardware designers in telecommunications and industrial markets to solve performance, power, cost and integration challenges with state-of-the-art 28nm programmable FPGAs, SoCs and 3D ICs. Prior to joining Xilinx (1994-2000) Jari worked as an Application Engineer at Mentor Graphics (FINLAND) Oy. After graduation he worked as Research Scientist in Computer Systems laboratory in Tampere University of Technology.

Partially Reconfigurable ASIPs
Prof. Gerd Ascheid, RWTH Aachen University, Germany

Highest throughput and energy efficiency is achieved with dedicated hardware, highest flexibility is provided by processors. Processors with application specific instruction sets (ASIP) trade some flexibility for more efficiency and throughput. On the other hand, coarse grained reconfigurable arrays (CGRA) introduce some hardware flexibility at the cost of efficiency and throughput. Combining both approaches allows building systems with the flexibility of programmable architecture yet achieving throughput and energy efficiency close to dedicated hardware (ASIC) solutions. The talk will discuss architectural options for the CGRA and its integration into the processor architecture, implementation issues and a design flow both for the pre- and post-silicon design phases. Following a general review of these points, specific examples for reconfigurable ASIPs will be discussed in some depth, in particular, an ASIP for MIMO processing in mobile communications.

Gerd Ascheid
Gerd Ascheid received his Diploma and PhD degrees in Electrical Engineering from RWTH Aachen University. In 1988 he started as a co-founder CADIS GmbH which successfully brought the system simulation tool COSSAP to the market. From 1994-2003 Gerd Ascheid was Director / Senior Director with Synopsys, Inc. In 2002 he was a co-founder of LisaTek whose processor design tools are now part of the Synopsys product portfolio. Since April 2003 Gerd Ascheid heads the Institute for Integrated Signal Processing Systems at RWTH Aachen University. He is also coordinator of the UMIC (Ultra-high speed Mobile Information and Communication) Research Centre at RWTH Aachen University. His research interest is in wireless communication algorithms and application specific integrated platforms, in particular, for mobile terminals.