International Symposium on System-on-Chip
SoC | 1999 | 2000 | 2001 | 2002 | 2003 | 2004 | 2005 | 2006 | 2007 | 2008 | 2009 | 2010 | 2011 | 2012 | 2013 | 2014 | 2015

General

Conference

Lodging / Travel


Valid XHTML 1.1

Valid CSS!

Preliminary Program

SoC 2013 Tampere

The following papers have been accepted for either oral or poster presentation.

    Oral presentation


Split-Cost Communication Model for Improved MPSoC Application Mapping 
Odendahl, Maximilian; Castrillon, Jeronimo; Volevach, Vitaliy; Leupers, Rainer; Ascheid, Gerd
RWTH Aachen University

Proactive Thermal-Budget-Based Beltway Routing Algorithm for Thermal-Aware 3D NoC Systems 
Kuo, Che-Chuan; Chen, Kun-Chih; Chang, En-Jui; Wu, An-Yeu
National Taiwan University

System Interconnect Extensions For Fully Transparent Demand Paging In Low-Cost MMU-less
Embedded Systems 
Miorandi, Gabriele; Zuolo, Lorenzo; Bertozzi, Davide; Zambelli, Cristian; Olivo, Piero
University of Ferrara

Optimizing the Overhead for Network-on-Chip Routing Reconfiguration in Massively Parallel 
Multi-Core Platforms 
Balboni, Marco; Triviño, Francisco; Flich, Josè; Bertozzi, Davide
University of Ferrara

TNODE: A Low Power Sensor Node Processor for Secure Wireless Networks 
Panic, Goran; Schrape, Oliver; Basmer, Thomas; Vater, Frank; Tittelbach-Helmrich, Klaus
IHP

Dependency Analysis and Visualization Tool for Kactus2 IP-XACT Design Framework 
Määttä, Joni-Matti Kristian; Honkonen, Mikko; Korhonen, Tommi; Salminen, Erno;
Hämäläinen, Timo D.
Tampere University of Technology

Implementation and evaluation of configuration scrubbing on CGRAs: A case study 
Jafri, Syed Mohammad Asad Hassan; Piestrak, Stanislaw; Hemani, Ahmed; Paul, Kolin; Plosila, Juha; 
Tenhunen, Hannu
Royal Institute of Technology (KTH) 

A cycle accurate simulation framework for asynchronous NoC design 
Terraneo, Federico; Zoni, Davide; Fornaciari, William
Politecnico di Milano

Extending IP-XACT to embedded system HW/SW integration 
Kamppi, Antti; Matilainen, Lauri; Määttä, Joni-Matti; Salminen, Erno; Hämäläinen, Timo D.
Tampere University of Technology

Crosstalk Avoidance Coding for Reliable Data Transmition of Network on Chips 
Shirmohammadi, Zahra; Miremadi, Seyed Ghassem
Sharif University

Prefetching Across a Shared Memory Tree within a Network-on-Chip Architecture 
Garside, Jamie; Audsley, Neil C
University of York

ViSA: A Highly Efficient Slot Architecture Enabling Multi-Objective ASIP Cores 
Figuli, Peter; Tradowsky, Carsten; Gaertner, Nadine; Becker, Juergen
Karlsruhe Institute of Technology

Scheduling of Parallelized Synchronous Dataflow Actors 
Zhou, Zheng; Desnos, Karol; Pelcat, Maxime; Nezan, Jean-François; Plishker, William; 
Bhattacharyya, Shuvra S.
University of Maryland

Study of Adaptive Detection for MIMO-OFDM Systems 
Suikkanen, Essi; Janhunen, Janne; Shahabuddin, Shahriar; Juntti, Markku
University of Oulu

A Family of Modular Area- and Energy-Efficient QRD-Accelerator Architectures 
VISHNOI, UPASNA; NOLL, TOBIAS G.
RWTH AACHEN UNIVERSITY

On the performance and synchronization of SW and HW Nelder-Mead implementations 
Mariano, Artur
Technische Universität Darmstadt

    Poster presentation


Efficient Distributed Memory Management in a Multi-Core H.264 Decoder on FPGA 
Zhang, Jiajie; Yu, Zheng; Yu, Zhiyi; Zhang, Kexin; Lu, Zhonghai; Jantsch, Axel
Fudan University

Framework for Industrial Embedded System Product Development and Management 
Leppäkoski, Arttu Ville Juhani; Hämäläinen, Timo D.; Salminen, Erno
Konecranes Plc

A Novel SAD Architecture for Variable Block Size Motion Estimation in HEVC Video Coding 
Nalluri, Purnachand; Nero Alves, Luis; Navarro, Antonio
Universidade de Aveiro, Instituto de Telecomunicações

Comparison of Analog Transactions using Statistics 
Rath, Alexander Wolfgang; Esen, Volkan; Ecker, Wolfgang
Infineon Technologies AG

Efficient On-chip Vector Processing for Multicore Processors 
Beldianu, Spiridon; Ziavras, Sotirios
New Jersey Institute of Technology

On the Impact of Dynamic Data Management for Distributed Local Memories in 
Heterogeneous MPSoCs 
Nöthen, Benedikt; Arnold, Oliver; Fettweis, Gerhard
TU Dresden

FPGA-ACCELERATED COLOR EDGE DETECTION USING A GEOMETRIC-ALGEBRA-TO-VERILOG COMPILER 
Stock, Florian; Koch, Andreas; Hildenbrand, Dietmar
Technical University Darmstadt

Partitioning Constraints and Iterative Routing Approach for Multi-FPGA Prototyping Platform 
TURKI, Mariem; Marrakchi, Zied; Mehrez, Habib; Abid, Mohamed
LIP6

Adaptive QoS Techniques for NoC-Based MPSoCs 
Moraes, Fernando; Ruaro, Marcelo; Carara, Everton
PUCRS 	

Achieving QoS in NoC-based MPSoCs through Dynamic Frequency Scaling 
Moraes, Fernando; Guindani, Guilherme
PUCRS

Evaluating the Scalability of Test Buses 
Amory, Alexandre Moraes; Moreira, Matheus Trevisan; Lazzari, Cristiano; Lubaszewski, Marcelo; 
Calazans, Ney; Moraes, Fernando
PUCRS